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| XILINX APPLICATIONS NOTE XAPP009V-V2.00                    BN-3-30-94 |
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README file for the XC3000A Harmonic Frequency Synthesizer:
===========================================================

Note: A more detailed description of this application can be found in
Section 8 of the Xilinx Data Book.

Files included in XAPP009V.ZIP:
-------------------------------
  
  README          This readme file
  HFS16\          This directory contains the Frequency Synthesizer
  FSK1011\        This directory contains the FSK Modulator   

HFS16 
-----

This 16-bit Harmonic Frequency Synthesizer uses an accumulator technique to
generate frequencies which are evenly-spaced harmonics of some minimum 
frequency. Extensive pipelining is employed to permit clock rates of up to
123 MHz in an XC3000A-6, and 213 MHz in an XC3100A-3. The macro uses two CLBs 
per bit. 
 
Design files included in directory HFS16:

  SCH\HFS16.1     Top-level Viewlogic V4..1.3a schematic, sheet 1
  SCH\HFS16.2     Top-level Viewlogic V4.1.3a schematic, sheet 2
  SCH\BITSLICE.1  Bit-slice of the HFS16 (Sheet 1)
  SCH\BITSLICE.2  CLBMAPs for the bit-slice (Sheet 2)
  SYM\*.1         Viewlogic Symbols for HFS 
  WIR\*.1         Viewlogic Wire files

  XNF\            Xilinx Netlists 
  HFS16.CST       Constraints file to lock CLBs in place
  HFS16.LCA       Placed and routed LCA file
  HFS16.XRP       Xdelay timing report using XC3000A-6

Software Versions used:

  DS390 Version 4.1.3a Viewlogic and Interface

Implementation Hints:

The CLBs are organized in a two columns by 16 rows CLB matrix. The advantage 
hereby is that the speed critical path can be implemented in adjacent CLBs 
with no interconnect delay. 

The critical path of the design is determined by the Carry net and the
load net. Therefore, if the CLBs are organized in a 2 by 8 array, the maximum 
speed is limited by the shift rate of the LCA.

To guarantee optimal partitioning of the holding register and the adder
logic, CLBMAPs were used in BITSLICE. The pins were locked to gain access
to direct interconnect, which has no routing delay.

Note: If a different layout is desired, the PIN LOCK attribute should be
deleted from the schematic to allow PPR to determine the best possible 
routing.

The following is a sample constraints file that organizes the 32 CLBs
in a 2 by 8 matrix in an XC3090:

  place block BIT0/D_INT : aa;
  place block BIT0/Q : ab;
  place block BIT1/D_INT : ba;
  place block BIT1/Q : bb;
  place block BIT2/D_INT : ca;
  place block BIT2/Q : cb;
	     .
	     .
	     .

Performance:

XDELAY was used to report all clock-to-set-up paths. See the .XRP file.

=============================================================================
 
FSK1011
-------

The 10/11 MHz FSK Modulator design is a modification of the frequency 
synthesizer that automatically switches between two frequencies in accordance 
with an NRZ input. The clock speed is 64 MHz.
The macro uses ten CLBs and one flip-flop. 
 
Design files included in directory FSK1011:

  SCH\FSK1011.1   Top-level Viewlogic V4.1.3a schematic
  SCH\FSKSLICE.1  Bit-slice of the FSK1011   (Sheet 1)
  SCH\FSKSLICE.2  CLBMAPs for the bit-slice  (Sheet 2)
  SYM\*.1         Viewlogic Symbols for FSK1011 
  WIR\*.1         Viewlogic Wire files

  XNF\            Xilinx Netlists 
  FSK1011.CST     Constraints file to lock CLBs in place
  FSK1011.LCA     Placed and routed LCA file
  FSK1011.XRP     Xdelay timing report file using XC3000A-6


Software Versions used:

  DS390 Version 4.1.3a Viewlogic and Interface

Implementation Hints:

The CLBs are organized in a 2-columns-by-5-rows CLB matrix. 
The advantage hereby is that the speed critical path can be 
implemented in adjacent CLBs with little interconnect delay. 

To guarantee optimal partitioning of the holding register and the adder
logic, CLBMAPs were used in BITSLICE. The pins were locked to gain access
to direct interconnect, which has no additional routing delay.

Note: If a different layout is desired, the PINLOCK attributes should be
deleted from the schematic to allow APR to determine the best possible 
routing.

The use of a placement constraints file increases the speed compared to 
PPR automatic placement. 

The following is a sample constraints file that organizes the 10 CLBs
in a 2 by 5 matrix in an XC3030:

  place block BIT0/D_INT : aa;
  place block BIT0/Q : ab;
  place block BIT1/D_INT : ba;
  place block BIT1/Q : bb;
  place block BIT2/D_INT : ca;
  place block BIT2/Q : cb;
	     .
	     .
	     .

--------------------------------- EOF -------------------------------

