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| XILINX APPLICATIONS XAPP001V:  CPIP8-V2.00                 BN-3-16-94 |
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README file for the XC3000A Counter CPIP8:
==========================================

Note: A more detailed description of this application can be found in 
Section 8 of the Xilinx Data Book.

CPIP8
-----

  This counter is an 8-bit binary up counter with a Clock Enable (CE) and an
asynchronous reset (RST).  It decodes the lower 3 bits of the counter at a
value of 6.  This value is pipelined because it will be sent to the upper
bits of the counter as a parallel enable along with the CE input.  In the
low level symbol, this pipelined enable is called CEO.  The counter is broken
into 3-bit sections as described in the application note in the Data Book.  
CEO is pipelined to achieve speeds of 105 MHz in the XC3000A-6 and  173 MHz 
in the XC3100A-3.  Because a high-level schematic was used, the CLB and net 
names have the prefix CPIPA/ in front of them. The .LCA file contains hand 
placement and routing to illustrate the preferred organization in the FPGA.


Design files included in directory CPIP8:

  README          This README file
  SCH\CPIP8H.1    Top-level Viewlogic V4.1.3a schematic
  SCH\CPIP8.1     8-Bit Up counter with Pipelined TC (CEO) (Sheet 1)
  SYM\*.1         Viewlogic Symbols
  WIR\*.1         Viewlogic wire file
  
  XNF\            Xilinx Netlists for High Level Schematic
  CPIP8H.CST      Placement constraints file
  CPIP8H.LCA      Placed and Routed LCA file
  CPIP8H.XRP      Xdelay timing report using XC3000A-6

Software Versions used:
  DS390 Version 4.1.3a Viewlogic and Interface


Recommended Layout, Routing:

  The recommended layout is shown below and is in the constraints file
CPIP8H.CST.  The placement for the 5 CLBs is in the upper left hand corner
in order to make the CPIPA/CEO (pipelined parallel enable) from CLB Q2 have
the shortest routing to the other CLBs.

;SamplePlacement Constraints File:
place block Q0 : AA;
place block Q2 : BA;
place block Q3 : AB;
place block Q5 : BB;
place block Q6 : CB;

Performance:

   To analyze the performance using stand-alone XDELAY, only clock-to-
set-up paths from flip-flops Q0, Q1, Q2 and CPIPA/CEO need be considered.
All other paths have 8 clock periods in which to settle, and do not affect
performance.

--------------------------------- EOF ----------------------------------------

