===============================================================================

	TMS320C54x Code Generation Version 3.13 Release Notes 
	=====================================================

The purpose of the v3.13 release is to provide workarounds in the c54x
software tools for 2 silicon bugs; the so-called "nested fret" and
"write-pending" bugs.

NESTED FRET - nested calls do not work properly because of hardware problems 
===========   involving the FRET instruction.

Bug Description:

 Only one level of the far return can be implemented.  When there are
 nested far calls or interrupts, only the inner-most far return is executed
 correctly, while the outer or remaining far return(s) fail.  The effect on
 the XPC is that, while the first XPC that is restored is correct, the next
 XPC restored is not the correct XPC, but the XPC of the deepest nested
 context, and these two values alternate for the next FRET(E) instructions
 executed.

Affected Silicon: C549 V2.1 and C5410 V1.0


Software Workaround Details:
===========================

Shell switch:  -mb

When you compile with the switch -mb (along with -mf -v548), 
the compiler will, instead of emitting FRET instructions, emit
a branch to the label _fret549.  You will find this label in
the rts file fret549.asm.  The code at label _fret549 will
pop the return address from the stack into accumulator B;
the return to the caller is then performed via a branch-through-accumulator.

Alternate return sequences are provided at labels _frete549 and
_freti549.  The code at these labels provide a side-effect-free return;
i.e., all registers are preserved.  In addition, _frete549 will set
the INTM bit.

Note that upon execution of the branch-through-accumulator to the
caller, if the next instruction accesses the stack pointer, a
pipeline conflict may occur.  The compiler will ensure that no
such conflict occurs in compiled code.

When used with the assembler (stand-alone or via the shell), -mb will,
in addition, set the assembler flag " __no_fret" to aid in conditional assembly.

-mb is only effective when -mf -v548 are also used.


WRITE-PENDING - stores which begin 1 cycle apart, and double stores (DST),
=============   may not work properly.


Bug Description:

When both CPU and peripherals (such as HPI/BSP/McBSP/API/DMA) access 
to a same block of a Single Access RAM (SARAM), conflicts can occur. 
Conflict occurs when the DMA bus requests to access a SARAM and CPU executes
a dual store or back-to-back store instruction to store values to the
same SARAM block. This conflict causes a wrong value to be written in the 
memory for the second store instruction (same as the first store value).


Affected Silicon: C549 V2.1 and C5410 V1.0



Software Workaround Details:
===========================

Shell switch: -mt

When you compile with the switch -mt, the compiler will change DST
instructions into single-store pairs (STH,STL).  The compiler will also make
sure that there is more than 1 cycle between any 2 store instructions.

When used with the assembler (stand-alone or via the shell), -mt will,
in addition, set the assembler flag "__stores_bug" to aid in conditional
assembly.

RTS
===
The runtime library included in this release was compiled for _both_
silicon bugs; i.e., it contains the workarounds for both the nested fret
and write-pending bugs.  To create a runtime which contains only one
of the workarounds, rebuild the library with the appropriate command-line
switch (-mb or -mt).  The library-make utility mk500 is included in this release
to assist in rebuilding the runtime.


Installation
============

The following files will replace the same files installed from the V3.1 Code 
Generation Tools Release. 

Solaris and HP-UNIX:
contents:
  readme.txt
  asm500
  cl500
  cg500
  mk500
  rts_ext.lib
  rts_ext.src   



Windows 95/NT:
contents:
  readme.txt
  asm500
  cl500
  cg500
  mk500
  rts_ext.lib
  rts_ext.src   



