The following information is supplemental to the Developer's Kit User's
Guide and provides a description of the PLD equations.


3.2.4   PCI Card PLD Functionality

There are two socketed 22V10 PLDs on the PCI add-in card.  These two devices 
control access to the add-on registers of the S5933.  U1 and U4 control the 
pass-thru interface logic.  The PLDs are socketed to allow customized add-on 
logic to be implemented.  The following sections describe the PLD 
functionality.

There are four pass-thru regions defined for the developer's kit.  Each 
region has different characteristics with respect to add-on bus width, and 
access time for devices which may be implemented on the add-on.  It is left 
to the user to implement a peripheral or memory device on one of the 
piggyback cards as a source/destination for pass-thru accesses.


3.2.4.1   U1 - Pass-thru Cycle State Machine

U1 generates the following signals for the S5933:
	PTADR#  Pass-thru address strobe
	PTRDY#  Pass-thru access complete indicator
	Q3:0            State machine bits to keep U4 synchronized to U1
	RD#             S5933 read strobe
	WR#             S5933 write strobe
	SA1:0           Address bits 1 and 0 generated from S5933 PTBE# 
			outputs for accessing 8- or 16-bit add-on devices.

Intermediate Variables are defined within the code to simplify some of the 
equations.  The following intermediate variables are defined:
	DONE            Decode of PTBE[3:0]#.  Indicates all pass-thru bytes 
			have been read.
	SLOW8           Decode of PTNUM1:0.  Indicates Base Address Region 1 
			has been accessed.
	SLOW16          Decode of PTNUM1:0.  Indicates Base Address Region 2 
			has been accessed.
	MED32           Decode of PTNUM1:0.  Indicates Base Address Region 3 
			has been accessed.
	FAST32          Decode of PTNUM1:0.  Indicates Base Address Region 4 
			has been accessed.

When the ISA card is installed (ISA = 0), The RD# and WR# outputs are floated.  
PTRDY# is also held asserted.

The pass-thru state machine is triggered when PTATN# is asserted and goes 
idle after PTRDY# is generated, completing a pass-thru access.  Table 1 shows 
the S5933 inputs asserted during the corresponding states of the state 
machine.  The state machine functions as follows:

State S0:  The state machine initializes to S0 at reset.  It remains in S0 
	until PTATN# is asserted by the S5933 (indicating a pass-thru access).  
	When PTATN# is asserted, the state machine advances to S1.

State S1:  S1 is the address phase for the add-on access.  PTADR# is asserted 
	during this state.  After one clock, the state machine advances to 
	S2.

State S2:  S2 is an idle clock.  The state machine advances based on which 
	pass-thru region has been accessed:  SLOW8 and SLOW16 accessed 
	advance to S3, MED32 accesses advance to S5, FAST32 accesses advance 
	to S6.

State S3:  Only SLOW8 and SLOW16 accesses enter S3.  The state machine 
	advances to S4 after one clock.

State S4:  Only SLOW8 and SLOW16 accesses enter S4.  The state machine 
	advances to S6 after one clock.

State S5:  Only SLOW8, SLOW16 and MED32 accesses enter S5.  The state machine 
	advances to S6 after one clock.

State S6:  All access eventually advance to S6.  For accesses to regions 
	which are not 32-bits (SLOW8 and SLOW16), the PTBE[3:0]# inputs are 
	monitored.  If any remain asserted, the state machine advances to S7.  
	If all PTBE[3:0]# inputs are deasserted, the state machine advances 
	to S8.  For MED32 and FAST32 accesses, PTBURST# is monitored.  If 
	asserted, the state machine advances to S2 (to continue the burst).  
	If PTBURST# is deasserted, the state machine returns to S0 (idle).

State S7:  Only SLOW8 and SLOW16 accesses enter S7.  This is an extra clock 
	to keep the command inputs to the S5933 inactive for a second clock.  
	PTATN# is monitored.  If asserted, the state machine advances to S2.  
	If PTATN# is deasserted, the state machine returns to S0 (idle).

State S8: Only SLOW8 and SLOW16 accesses enter S8.  Because all of the 
	PTBE[3:0]# outputs are deasserted, PTBURST# can be sampled to 
	determine if a PCI burst is occurring.  If PTBURST# is asserted, the 
	state machine advances to S2 (to continue the burst).  If PTBURST# is 
	deasserted, the state machine returns to S0 (idle).


State #         SLOW8           SLOW16          MED32           FAST32
-----------------------------------------------------------------------------
S0              ---             ---             SELECT# (1)     SELECT# (1)

S1              PTADR#          PTADR#          PTADR#          PTADR#

S2              ---             ---             ---             SELECT# (2)

S3              RD#/WR#         RD#/WR#         ---             ---
		SELECT#         SELECT#

S4              RD#/WR#         RD#/WR#         ---             ---
		SELECT#         SELECT#

S5              RD#/WR#         RD#/WR#         RD#/WR#         ---
		SELECT#         SELECT#         SELECT#

S6              RD#/WR#         RD#/WR#         RD#/WR#         RD#/WR#
		SELECT#         SELECT#         SELECT#         SELECT#
		BE[3:0]# (3)    BE[3:0]# (3)    BE[3:0]#        BE[3:0]# 
		PTRDY# (4)      PTRDY# (4)      PTRDY#          PTRDY# 

S7              SELECT#         SELECT#         ---             ---

S8              SELECT#         SELECT#         ---             ---

	Table 1.  State Machine Outputs Asserted by State

(1) Only after the last data phase of a transfer (for one clock)
(2) Only on the second or later data phase of a pass-thru burst
(3) For SLOW8, only one is asserted at a time, for SLOW16, only two are 
    asserted at a time
(4) Only if all pass-thru byte enables are deasserted


3.2.4.2   U4 - Pass-thru Data Register Access State Machine

U4 is used to support U1 to generate control inputs to the S5933.  U4 asserts
the BE[3:0]# inputs, the SELECT# input, and the ADR6:2 inputs to the S5933. 
These are synchronized to the U1 state machine via the Q3:0 inputs (which 
indicate the current state of the U1 machine).  The ADR6:2 inputs are fixed 
at the pass-thru data register address.  SELECT# and BE[3:0]# are asserted 
as indicated in Table 1.

The equations for the byte enables allow accesses to 8-bit and 16-bit regions
(SLOW8 and SLOW16) to cycle through the byte enables.  In this way, a single 
32-bit PCI pass-thru access is broken into multiple 8- or 16-bit accesses on 
the add-on interface.  During a SLOW8 access, byte enables can only be 
asserted if all of the PTBE's below it are deasserted (i.e., only assert BE3#
if PTBE[2:0]# are deasserted).  For SLOW16 accesses, BE[3:2]# can only be 
asserted in PTBE[1:0]# are deasserted.

When the ISA card is installed (ISA = 0), the BE[3:0]#, SELECT# and ADR6:2 
outputs are floated.

3.4.3   IU3 - ISA Card PLD 

IU3 is a socketed 22V10 on the ISA card which takes care of ISA bus address 
decoding and generating S5933 add-on bus cycles from ISA bus cycles.  The PLD
equations can be easily modified to decode different addresses in ISA bus I/O
space should a system address conflict occur.

IU3 decodes ISA bus cycles used to access add-on operation registers of the 
S5933.  ISA address lines, IOR (I/O read), IOW (I/O write), AEN (address 
enable) and SBHE (byte high enable) are monitored.  

When the ISA card is installed, the byte enables to the S5933 are driven by 
IU3.  These are a function of SA1, SA0, and SBHE.  The S5933 RD#, WR#, and 
SELECT# inputs are also driven by IU3 as a function of IOR, IOW and an 
address decode.

The ISA card maps itself into ISA I/O space.  The S5933 operation 
registers are mapped to 300h-33Fh with the add-on transfer count registers 
mapped at 718h and 71Ch

