
0: CSR
	0	19"/15" mode
	1	unused
	2	Enable Video output
	3	Or/And cursor function
	4	Enable video loopback
	5	Loopback test bit
	6	Interrupt enable
	7	On/Off cursor
	8	Closed/Open mouse switch A
	9	Closed/Open mouse switch B
	10	Closed/Open mouse switch C
	11	Memory bank switch 0
	12	Memory bank switch 1
	13	Memory bank switch 2
	14	Memory bank switch 3
	15	unused
2: Cursor X position
	9:0	Cursor X position
4: Mouse position register
	7:0	X count
	15:0	Y count
6: unused
8: CRTC address pointer register
	4:0	Internal register address
	    0	Horiz Total		Num of character times in a line
	    1	Horiz Displayed		Num of displayed characters in a line
	    2	Hsync Position		Num of char times until Hsync
	    3	Hsync/Vsync Widths	Four bits for each sync width
	    4	Vert Total		Num of char rows per screen
	    5	Vert Total Adjust	Num of scan lines to finish the screen
	    6	Vert Displayed		Num of char rows to be displayed
	    7	Vert Sync Position	Num of char rows until vert sync
	    8	Mode			Addressing, Interlace, and Cursor
	    9	Max Scan Line		Num of scan lines in a char row
	    10	Cursor Scan Start	Scan line in which cursor starts
	    11	Cursor Scan End		When the cursor ends
	    12	Start Address High	Where to start memory
	    13	Start Address Low	    in CRT refresh process
	    14	Cursor Address High	Where to position the cursor in memory
	    15	Cursor Address Low
	    16	Light Pen Position High	Position of the light pen
	    17	Light Pen Position Low
	5	Vertical blanking
	6	Light pen register full
	7	Update strobe
10: CRTC data register
	7:0	Data to/from the register selected by the CRTC address
12: Interrupt controller data register
	7:0	Data to/from the selected interrupt register
	    When referring to a level:
		0	(highest) UART
		1	Vsync
		2	Mouse
		3	Cusor Start
		4	Mouse Switch A
		5	Mouse Switch B
		6	Mouse Switch C
		7	(lowest) unused
	    Interrupt Request Register (IRR)
		0:7	bit map of pending interrupts
	    Interrupt Service Register (ISR)
		0:7	bit map of acknowledge status of the IRR bits
	    Interrupt Mask Register (IMR)
		0:7	bit map of interrupts to be masked
	    Auto Clear Register
		0:7	bit map of ISR bits to autoclear
	    Mode register
		7	Enable/Disable group interrupts
		6:5	Register preselect
		    00	ISR
		    01	IMR
		    10	IRR
		    11	ACR
		4	MBZ
		3	MBZ
		2	Interrupt/polled mode
		1	Use One/Multiple Vectors to interrupt with
		0	Rotating/Fixed priorities
14: Interrupt controller CSR (ICSR)
    Read:
	2:0	number of highest unmasked bit in IRR, valid if bit 7 is clear
	3	Group interrupts enabled, from Mode bit 7
	4	Polled/Interrupt mode, from Mode bit 2
	5	Rotating/Fixed priority, from Mode reg bit 0
	6	Enable, unused
	7	When clear, indicates that an unmasked bit in the IRR is set
    Write:
    	7:0	Command
	    00000000	Reset: Set IMR, clear IRR, ISR, ACR, and mode reg
	    00010xxx	Clear IRR and IMR
	    00011abc	Clear bit abc in IRR and IMR
	    0010????	Unknown to me, used in Ultrix, seems like clear IMR bit
	    00110xxx	Set the IMR to all 1's
	    00111abc	Set bit abc in IMR
	    01000xxx	Clear IRR
	    01001abc	Clear bit abc in IRR
	    01010xxx	Set the IRR to all ones
	    01011abc	Set bit abc in IRR
	    0110xxxx	Clear the highest priority bit in the ISR
	    01110xxx	Clear ISR
	    01111abc	Clear bit abc in ISR
	    100abcde	Set low 5 bits of Mode register to abcde
	    1010abcd	Set bits 5 and 6 of Mode to ab, bit 7 by cd as
		00  No change to bit 7
		01  Set bit 7
		10  Clear bit 7
		11  Illegal
	    1011xxxx	Writes to Data reg to go to IMR
	    1100xxxx	Writes to Data reg to go to ACR
	    11100abc	Writes to Data reg to go to response memory by abc as
		000 level 0
		001 level 1
		010 level 2
		011 level 3
		100 level 4
		101 level 5
		110 level 6
		111 level 7
16-31: unused
32: UART mode regs 1A and 2A (registers loaded successively to same address)
    1A:
	0:1	bits per character (11 = 8 bits)
	2	Odd/Even parity
	3:4	Parity mode (10 = no parity)
	5	Block/? error mode
	6	FIFO full Rx interrupt select
	7	Disable/Enable Rx RTS control
    2A:
	0:3	Stop bit length (0111 = one bit)
	4	Disable/Enable Tx CTS
	5	Disable/Enable Tx RTS control
	6:7	Channel mode (00 = normal)
34: Status/Clock Select register A
    Read:
	0	Receiver ready
	1	FIFO full
	2	Transmitter ready
	3	Transmitter empty
	4	Overrun error
	5	Parity error
	6	Framing error
	7	Received break
    Write:
	0:3	Tx Clock select
	4:7	Rx Clock select
36: Command register A
	0	Enable Rx
	1	Disable Rx
	2	Enable Tx
	3	Disable Tx
	4:6	Misc commands
	    000 - NOP
	    001 - Reset mode register pointer
	    010 - Reset Receiver
	    011 - Reset Transmitter
	    100 - Reset error status
	    101 - Reset Channel A break change interrupt
	    110 - Start break
	    111 - Stop break
	7	MBZ
38: Transmit/Receive buffer A
    Read:
	7:0	Receive Buffer
    Write:
	7:0	Transmit Buffer
40: unused
42: Interrupt Status/Mask register
    Read:
	0	Tx A interrupt
	1	Rx/FIFO full A interrupt
	2	Delta break A
	3	Counter ready interrupt
	4	Tx B interrupt
	5	Rx/FIFO full B interrupt
	6	Delta break B
	7	Input port change
    Write:
	0:7	Interrupt mask register for above bits
44-46: unused
48: UART mode regs 1B and 2B (registers loaded successively to same address)
    1A:
	0:1	bits per character (11 = 8 bits)
	2	Odd/Even parity
	3:4	Parity mode (10 = no parity)
	5	Block/? error mode
	6	FIFO full Rx interrupt select
	7	Disable/Enable Rx RTS control
    2A:
	0:3	Stop bit length (0111 = one bit)
	4	Disable/Enable Tx CTS
	5	Disable/Enable Tx RTS control
	6:7	Channel mode (00 = normal)
50: Status/Clock Select register B
    Read:
	0	Receiver ready
	1	FIFO full
	2	Transmitter ready
	3	Transmitter empty
	4	Overrun error
	5	Parity error
	6	Framing error
	7	Received break
    Write:
	0:3	Tx Clock select
	4:7	Rx Clock select
52: Command register B
	0	Enable Rx
	1	Disable Rx
	2	Enable Tx
	3	Disable Tx
	4:6	Misc commands
	    000 - NOP
	    001 - Reset mode register pointer
	    010 - Reset Receiver
	    011 - Reset Transmitter
	    100 - Reset error status
	    101 - Reset Channel A break change interrupt
	    110 - Start break
	    111 - Stop break
	7	MBZ
54: Transmit/Receive buffer B
    Read:
	7:0	Receive Buffer
    Write:
	7:0	Transmit Buffer
56-62: unused



