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decoder.c
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1 /*
2 * $Id: decoder.c,v 1.36 2008/01/06 22:38:18 joerg_wunsch Exp $
3 *
4 ****************************************************************************
5 *
6 * simulavr - A simulator for the Atmel AVR family of microcontrollers.
7 * Copyright (C) 2001, 2002, 2003 Theodore A. Roth
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 *
23 ****************************************************************************
24 */
25
26 /**
27 * \file decoder.c
28 * \brief Module for handling opcode decoding.
29 *
30 * The heart of the instruction decoder is the decode_opcode() function.
31 *
32 * The decode_opcode() function examines the given opcode to
33 * determine which instruction applies and returns a pointer to a function to
34 * handler performing the instruction's operation. If the given opcode does
35 * not map to an instruction handler, NULL is returned.
36 *
37 * Nearly every instruction in Atmel's Instruction Set Data Sheet will have a
38 * handler function defined. Each handler will perform all the operations
39 * described in the data sheet for a given instruction. A few instructions
40 * have synonyms. For example, CBR is a synonym for ANDI.
41 *
42 * This should all be fairly straight forward.
43 */
44
45 #include <config.h>
46
47 #include <stdio.h>
48 #include <stdlib.h>
49
50 #include "avrerror.h"
51 #include "avrmalloc.h"
52 #include "avrclass.h"
53 #include "utils.h"
54 #include "callback.h"
55 #include "op_names.h"
56
57 #include "storage.h"
58 #include "flash.h"
59
60 #include "vdevs.h"
61 #include "memory.h"
62 #include "stack.h"
63 #include "register.h"
64 #include "sram.h"
65 #include "eeprom.h"
66 #include "timers.h"
67 #include "ports.h"
68
69 #include "avrcore.h"
70
71 #include "decoder.h"
72
73 struct opcode_info *global_opcode_lookup_table;
74
75 /** \brief Masks to help extracting information from opcodes. */
76
77 enum decoder_operand_masks
78 {
79 /** 2 bit register id ( R24, R26, R28, R30 ) */
80 mask_Rd_2 = 0x0030,
81 /** 3 bit register id ( R16 - R23 ) */
82 mask_Rd_3 = 0x0070,
83 /** 4 bit register id ( R16 - R31 ) */
84 mask_Rd_4 = 0x00f0,
85 /** 5 bit register id ( R00 - R31 ) */
86 mask_Rd_5 = 0x01f0,
87
88 /** 3 bit register id ( R16 - R23 ) */
89 mask_Rr_3 = 0x0007,
90 /** 4 bit register id ( R16 - R31 ) */
91 mask_Rr_4 = 0x000f,
92 /** 5 bit register id ( R00 - R31 ) */
93 mask_Rr_5 = 0x020f,
94
95 /** for 8 bit constant */
96 mask_K_8 = 0x0F0F,
97 /** for 6 bit constant */
98 mask_K_6 = 0x00CF,
99
100 /** for 7 bit relative address */
101 mask_k_7 = 0x03F8,
102 /** for 12 bit relative address */
103 mask_k_12 = 0x0FFF,
104 /** for 22 bit absolute address */
105 mask_k_22 = 0x01F1,
106
107 /** register bit select */
108 mask_reg_bit = 0x0007,
109 /** status register bit select */
110 mask_sreg_bit = 0x0070,
111 /** address displacement (q) */
112 mask_q_displ = 0x2C07,
113
114 /** 5 bit register id ( R00 - R31 ) */
115 mask_A_5 = 0x00F8,
116 /** 6 bit IO port id */
117 mask_A_6 = 0x060F,
118 };
119
120 /* Some handlers need predeclared */
121 static int avr_op_CALL (AvrCore *core, uint16_t opcode, unsigned int arg1,
122 unsigned int arg2);
123 static int avr_op_JMP (AvrCore *core, uint16_t opcode, unsigned int arg1,
124 unsigned int arg2);
125 static int avr_op_LDS (AvrCore *core, uint16_t opcode, unsigned int arg1,
126 unsigned int arg2);
127 static int avr_op_STS (AvrCore *core, uint16_t opcode, unsigned int arg1,
128 unsigned int arg2);
129
130 /****************************************************************************\
131 *
132 * Helper functions to extract information from the opcodes.
133 *
134 \***************************************************************************/
135
136 static int
137 get_rd_2 (uint16_t opcode)
138 {
139 int reg = ((opcode & mask_Rd_2) >> 4) & 0x3;
140 return (reg * 2) + 24;
141 }
142
143 static int
144 get_rd_3 (uint16_t opcode)
145 {
146 int reg = opcode & mask_Rd_3;
147 return ((reg >> 4) & 0x7) + 16;
148 }
149
150 static int
151 get_rd_4 (uint16_t opcode)
152 {
153 int reg = opcode & mask_Rd_4;
154 return ((reg >> 4) & 0xf) + 16;
155 }
156
157 static int
158 get_rd_5 (uint16_t opcode)
159 {
160 int reg = opcode & mask_Rd_5;
161 return ((reg >> 4) & 0x1f);
162 }
163
164 static int
165 get_rr_3 (uint16_t opcode)
166 {
167 return (opcode & mask_Rr_3) + 16;
168 }
169
170 static int
171 get_rr_4 (uint16_t opcode)
172 {
173 return (opcode & mask_Rr_4) + 16;
174 }
175
176 static int
177 get_rr_5 (uint16_t opcode)
178 {
179 int reg = opcode & mask_Rr_5;
180 return (reg & 0xf) + ((reg >> 5) & 0x10);
181 }
182
183 static uint8_t
184 get_K_8 (uint16_t opcode)
185 {
186 int K = opcode & mask_K_8;
187 return ((K >> 4) & 0xf0) + (K & 0xf);
188 }
189
190 static uint8_t
191 get_K_6 (uint16_t opcode)
192 {
193 int K = opcode & mask_K_6;
194 return ((K >> 2) & 0x0030) + (K & 0xf);
195 }
196
197 static int
198 get_k_7 (uint16_t opcode)
199 {
200 return (((opcode & mask_k_7) >> 3) & 0x7f);
201 }
202
203 static int
204 get_k_12 (uint16_t opcode)
205 {
206 return (opcode & mask_k_12);
207 }
208
209 static int
210 get_k_22 (uint16_t opcode)
211 {
212 /* Masks only the upper 6 bits of the address, the other 16 bits
213 * are in PC + 1. */
214 int k = opcode & mask_k_22;
215 return ((k >> 3) & 0x003e) + (k & 0x1);
216 }
217
218 static int
219 get_reg_bit (uint16_t opcode)
220 {
221 return opcode & mask_reg_bit;
222 }
223
224 static int
225 get_sreg_bit (uint16_t opcode)
226 {
227 return (opcode & mask_sreg_bit) >> 4;
228 }
229
230 static int
231 get_q (uint16_t opcode)
232 {
233 /* 00q0 qq00 0000 0qqq : Yuck! */
234 int q = opcode & mask_q_displ;
235 int qq = (((q >> 1) & 0x1000) + (q & 0x0c00)) >> 7;
236 return (qq & 0x0038) + (q & 0x7);
237 }
238
239 static int
240 get_A_5 (uint16_t opcode)
241 {
242 return (opcode & mask_A_5) >> 3;
243 }
244
245 static int
246 get_A_6 (uint16_t opcode)
247 {
248 int A = opcode & mask_A_6;
249 return ((A >> 5) & 0x0030) + (A & 0xf);
250 }
251
252 /****************************************************************************\
253 *
254 * Helper functions for calculating the status register bit values.
255 * See the Atmel data sheet for the instuction set for more info.
256 *
257 \****************************************************************************/
258
259 static int
260 get_add_carry (uint8_t res, uint8_t rd, uint8_t rr, int b)
261 {
262 uint8_t resb = res >> b & 0x1;
263 uint8_t rdb = rd >> b & 0x1;
264 uint8_t rrb = rr >> b & 0x1;
265 return (rdb & rrb) | (rrb & ~resb) | (~resb & rdb);
266 }
267
268 static int
269 get_add_overflow (uint8_t res, uint8_t rd, uint8_t rr)
270 {
271 uint8_t res7 = res >> 7 & 0x1;
272 uint8_t rd7 = rd >> 7 & 0x1;
273 uint8_t rr7 = rr >> 7 & 0x1;
274 return (rd7 & rr7 & ~res7) | (~rd7 & ~rr7 & res7);
275 }
276
277 static int
278 get_sub_carry (uint8_t res, uint8_t rd, uint8_t rr, int b)
279 {
280 uint8_t resb = res >> b & 0x1;
281 uint8_t rdb = rd >> b & 0x1;
282 uint8_t rrb = rr >> b & 0x1;
283 return (~rdb & rrb) | (rrb & resb) | (resb & ~rdb);
284 }
285
286 static int
287 get_sub_overflow (uint8_t res, uint8_t rd, uint8_t rr)
288 {
289 uint8_t res7 = res >> 7 & 0x1;
290 uint8_t rd7 = rd >> 7 & 0x1;
291 uint8_t rr7 = rr >> 7 & 0x1;
292 return (rd7 & ~rr7 & ~res7) | (~rd7 & rr7 & res7);
293 }
294
295 static int
296 get_compare_carry (uint8_t res, uint8_t rd, uint8_t rr, int b)
297 {
298 uint8_t resb = res >> b & 0x1;
299 uint8_t rdb = rd >> b & 0x1;
300 uint8_t rrb = rr >> b & 0x1;
301 return (~rdb & rrb) | (rrb & resb) | (resb & ~rdb);
302 }
303
304 static int
305 get_compare_overflow (uint8_t res, uint8_t rd, uint8_t rr)
306 {
307 uint8_t res7 = res >> 7 & 0x1;
308 uint8_t rd7 = rd >> 7 & 0x1;
309 uint8_t rr7 = rr >> 7 & 0x1;
310 /* The atmel data sheet says the second term is ~rd7 for CP
311 * but that doesn't make any sense. You be the judge. */
312 return (rd7 & ~rr7 & ~res7) | (~rd7 & rr7 & res7);
313 }
314
315 /****************************************************************************\
316 *
317 * Misc Helper functions
318 *
319 \****************************************************************************/
320
321 static int
322 is_next_inst_2_words (AvrCore *core)
323 {
324 /* See if next is a two word instruction
325 * CALL, JMP, LDS, and STS are the only two word (32 bit) instructions. */
326 uint16_t next_opcode =
327 flash_read (core->flash, avr_core_PC_get (core) + 1);
328 struct opcode_info *opi = decode_opcode (next_opcode);
329
330 return ((opi->func == avr_op_CALL) || (opi->func == avr_op_JMP)
331 || (opi->func == avr_op_LDS) || (opi->func == avr_op_STS));
332 }
333
334 static int
335 n_bit_unsigned_to_signed (unsigned int val, int n)
336 {
337 /* Convert n-bit unsigned value to a signed value. */
338 unsigned int mask;
339
340 if ((val & (1 << (n - 1))) == 0)
341 return (int)val;
342
343 /* manually calculate two's complement */
344 mask = (1 << n) - 1;
345 return -1 * ((~val & mask) + 1);
346 }
347
348 /****************************************************************************\
349 *
350 * Opcode handler functions.
351 *
352 \****************************************************************************/
353
354 static int
355 avr_op_ADC (AvrCore *core, uint16_t opcode, unsigned int arg1,
356 unsigned int arg2)
357 {
358 /*
359 * Add with Carry.
360 *
361 * Opcode : 0001 11rd dddd rrrr
362 * Usage : ADC Rd, Rr
363 * Operation : Rd <- Rd + Rr + C
364 * Flags : Z,C,N,V,S,H
365 * Num Clocks : 1
366 */
367 int H, V, N, S, Z, C;
368
369 int Rd = arg1;
370 int Rr = arg2;
371
372 uint8_t rd = avr_core_gpwr_get (core, Rd);
373 uint8_t rr = avr_core_gpwr_get (core, Rr);
374
375 uint8_t res = rd + rr + avr_core_sreg_get_bit (core, SREG_C);
376
377 uint8_t sreg = avr_core_sreg_get (core);
378
379 sreg = set_bit_in_byte (sreg, SREG_H, H = get_add_carry (res, rd, rr, 3));
380 sreg = set_bit_in_byte (sreg, SREG_V, V = get_add_overflow (res, rd, rr));
381 sreg = set_bit_in_byte (sreg, SREG_N, N = ((res >> 7) & 0x1));
382 sreg = set_bit_in_byte (sreg, SREG_S, S = (N ^ V));
383 sreg = set_bit_in_byte (sreg, SREG_Z, Z = ((res & 0xff) == 0));
384 sreg = set_bit_in_byte (sreg, SREG_C, C = get_add_carry (res, rd, rr, 7));
385
386 avr_core_sreg_set (core, sreg);
387
388 avr_core_gpwr_set (core, Rd, res);
389 avr_core_PC_incr (core, 1);
390 avr_core_inst_CKS_set (core, 1);
391
392 return opcode_ADC;
393 }
394
395 static int
396 avr_op_ADD (AvrCore *core, uint16_t opcode, unsigned int arg1,
397 unsigned int arg2)
398 {
399 /*
400 * Add without Carry.
401 *
402 * Opcode : 0000 11rd dddd rrrr
403 * Usage : ADD Rd, Rr
404 * Operation : Rd <- Rd + Rr
405 * Flags : Z,C,N,V,S,H
406 * Num Clocks : 1
407 */
408 int H, V, N, S, Z, C;
409
410 int Rd = arg1;
411 int Rr = arg2;
412
413 uint8_t rd = avr_core_gpwr_get (core, Rd);
414 uint8_t rr = avr_core_gpwr_get (core, Rr);
415
416 uint8_t res = rd + rr;
417
418 uint8_t sreg = avr_core_sreg_get (core);
419
420 sreg = set_bit_in_byte (sreg, SREG_H, H = get_add_carry (res, rd, rr, 3));
421 sreg = set_bit_in_byte (sreg, SREG_V, V = get_add_overflow (res, rd, rr));
422 sreg = set_bit_in_byte (sreg, SREG_N, N = ((res >> 7) & 0x1));
423 sreg = set_bit_in_byte (sreg, SREG_S, S = (N ^ V));
424 sreg = set_bit_in_byte (sreg, SREG_Z, Z = ((res & 0xff) == 0));
425 sreg = set_bit_in_byte (sreg, SREG_C, C = get_add_carry (res, rd, rr, 7));
426
427 avr_core_sreg_set (core, sreg);
428
429 avr_core_gpwr_set (core, Rd, res);
430 avr_core_PC_incr (core, 1);
431 avr_core_inst_CKS_set (core, 1);
432
433 return opcode_ADD;
434 }
435
436 static int
437 avr_op_ADIW (AvrCore *core, uint16_t opcode, unsigned int arg1,
438 unsigned int arg2)
439 {
440 /*
441 * Add Immediate to Word.
442 *
443 * Opcode : 1001 0110 KKdd KKKK
444 * Usage : ADIW Rd, K
445 * Operation : Rd+1:Rd <- Rd+1:Rd + K
446 * Flags : Z,C,N,V,S
447 * Num Clocks : 2
448 */
449 int C, Z, S, N, V;
450
451 int Rd = arg1;
452 uint8_t K = arg2;
453
454 uint8_t rdl = avr_core_gpwr_get (core, Rd);
455 uint8_t rdh = avr_core_gpwr_get (core, Rd + 1);
456
457 uint16_t rd = (rdh << 8) + rdl;
458 uint16_t res = rd + K;
459
460 uint8_t sreg = avr_core_sreg_get (core);
461
462 sreg = set_bit_in_byte (sreg, SREG_V, V =
463 (~(rdh >> 7 & 0x1) & (res >> 15 & 0x1)));
464 sreg = set_bit_in_byte (sreg, SREG_N, N = ((res >> 15) & 0x1));
465 sreg = set_bit_in_byte (sreg, SREG_S, S = (N ^ V));
466 sreg = set_bit_in_byte (sreg, SREG_Z, Z = ((res & 0xffff) == 0));
467 sreg = set_bit_in_byte (sreg, SREG_C, C =
468 (~(res >> 15 & 0x1) & (rdh >> 7 & 0x1)));
469
470 avr_core_sreg_set (core, sreg);
471
472 avr_core_gpwr_set (core, Rd, res & 0xff);
473 avr_core_gpwr_set (core, Rd + 1, res >> 8);
474
475 avr_core_PC_incr (core, 1);
476 avr_core_inst_CKS_set (core, 2);
477
478 return opcode_ADIW;
479 }
480
481 static int
482 avr_op_AND (AvrCore *core, uint16_t opcode, unsigned int arg1,
483 unsigned int arg2)
484 {
485 /*
486 * Logical AND.
487 *
488 * Opcode : 0010 00rd dddd rrrr
489 * Usage : AND Rd, Rr
490 * Operation : Rd <- Rd & Rr
491 * Flags : Z,N,V,S
492 * Num Clocks : 1
493 */
494 int Z, N, V, S;
495
496 int Rd = arg1;
497 int Rr = arg2;
498
499 uint8_t rd = avr_core_gpwr_get (core, Rd);
500 uint8_t rr = avr_core_gpwr_get (core, Rr);
501 uint8_t res = rd & rr;
502
503 uint8_t sreg = avr_core_sreg_get (core);
504
505 sreg = set_bit_in_byte (sreg, SREG_V, V = 0);
506 sreg = set_bit_in_byte (sreg, SREG_N, N = ((res >> 7) & 0x1));
507 sreg = set_bit_in_byte (sreg, SREG_S, S = (N ^ V));
508 sreg = set_bit_in_byte (sreg, SREG_Z, Z = ((res & 0xff) == 0));
509
510 avr_core_sreg_set (core, sreg);
511
512 avr_core_gpwr_set (core, Rd, res);
513 avr_core_PC_incr (core, 1);
514 avr_core_inst_CKS_set (core, 1);
515
516 return opcode_AND;
517 }
518
519 static int
520 avr_op_ANDI (AvrCore *core, uint16_t opcode, unsigned int arg1,
521 unsigned int arg2)
522 {
523 /*
524 * Logical AND with Immed.
525 *
526 * Opcode : 0111 KKKK dddd KKKK
527 * Usage : ANDI Rd, K
528 * Operation : Rd <- Rd & K
529 * Flags : Z,N,V,S
530 * Num Clocks : 1
531 */
532 int Z, N, V, S;
533
534 int Rd = arg1;
535 uint8_t K = arg2;
536
537 uint8_t rd = avr_core_gpwr_get (core, Rd);
538 uint8_t res = rd & K;
539
540 uint8_t sreg = avr_core_sreg_get (core);
541
542 sreg = set_bit_in_byte (sreg, SREG_V, V = 0);
543 sreg = set_bit_in_byte (sreg, SREG_N, N = ((res >> 7) & 0x1));
544 sreg = set_bit_in_byte (sreg, SREG_S, S = (N ^ V));
545 sreg = set_bit_in_byte (sreg, SREG_Z, Z = ((res & 0xff) == 0));
546
547 avr_core_sreg_set (core, sreg);
548
549 avr_core_gpwr_set (core, Rd, res);
550 avr_core_PC_incr (core, 1);
551 avr_core_inst_CKS_set (core, 1);
552
553 return opcode_ANDI;
554 }
555
556 static int
557 avr_op_ASR (AvrCore *core, uint16_t opcode, unsigned int arg1,
558 unsigned int arg2)
559 {
560 /*
561 * Arithmetic Shift Right.
562 *
563 * Opcode : 1001 010d dddd 0101
564 * Usage : ASR Rd
565 * Operation : Rd(n) <- Rd(n+1), n=0..6
566 * Flags : Z,C,N,V,S
567 * Num Clocks : 1
568 */
569 int Z, C, N, V, S;
570
571 int Rd = arg1;
572
573 uint8_t rd = avr_core_gpwr_get (core, Rd);
574 uint8_t res = (rd >> 1) + (rd & 0x80);
575
576 uint8_t sreg = avr_core_sreg_get (core);
577
578 sreg = set_bit_in_byte (sreg, SREG_N, N = ((res >> 7) & 0x1));
579 sreg = set_bit_in_byte (sreg, SREG_C, C = (rd & 0x1));
580 sreg = set_bit_in_byte (sreg, SREG_V, V = (N ^ C));
581 sreg = set_bit_in_byte (sreg, SREG_S, S = (N ^ V));
582 sreg = set_bit_in_byte (sreg, SREG_Z, Z = ((res & 0xff) == 0));
583
584 avr_core_sreg_set (core, sreg);
585
586 avr_core_gpwr_set (core, Rd, res);
587 avr_core_PC_incr (core, 1);
588 avr_core_inst_CKS_set (core, 1);
589
590 return opcode_ASR;
591 }
592
593 static int
594 avr_op_BCLR (AvrCore *core, uint16_t opcode, unsigned int arg1,
595 unsigned int arg2)
596 {
597 /*
598 * Clear a single flag or bit in SREG.
599 *
600 * Opcode : 1001 0100 1sss 1000
601 * Usage : BCLR
602 * Operation : SREG(s) <- 0
603 * Flags : SREG(s)
604 * Num Clocks : 1
605 */
606 avr_core_sreg_set_bit (core, arg1, 0);
607 avr_core_PC_incr (core, 1);
608 avr_core_inst_CKS_set (core, 1);
609
610 return opcode_BCLR;
611 }
612
613 static int
614 avr_op_BLD (AvrCore *core, uint16_t opcode, unsigned int arg1,
615 unsigned int arg2)
616 {
617 /* Bit load from T to Register.
618 *
619 * Opcode : 1111 100d dddd 0bbb
620 * Usage : BLD Rd, b
621 * Operation : Rd(b) <- T
622 * Flags : None
623 * Num Clocks : 1
624 */
625 int Rd = arg1;
626 int bit = arg2;
627
628 uint8_t rd = avr_core_gpwr_get (core, Rd);
629 int T = avr_core_sreg_get_bit (core, SREG_T);
630 uint8_t res;
631
632 if (T == 0)
633 res = rd & ~(1 << bit);
634 else
635 res = rd | (1 << bit);
636
637 avr_core_gpwr_set (core, Rd, res);
638 avr_core_PC_incr (core, 1);
639 avr_core_inst_CKS_set (core, 1);
640
641 return opcode_BLD;
642 }
643
644 static int
645 avr_op_BRBC (AvrCore *core, uint16_t opcode, unsigned int arg1,
646 unsigned int arg2)
647 {
648 /*
649 * Branch if Status Flag Cleared.
650 *
651 * Pass control directly to the specific bit operation.
652 *
653 * Opcode : 1111 01kk kkkk ksss
654 * Usage : BRBC s, k
655 * Operation : if (SREG(s) = 0) then PC <- PC + k + 1
656 * Flags : None
657 * Num Clocks : 1 / 2
658 *
659 * k is an relative address represented in two's complements.
660 * (64 < k <= 64)
661 */
662 int bit = arg1;
663 int k = arg2;
664
665 if (avr_core_sreg_get_bit (core, bit) == 0)
666 {
667 avr_core_PC_incr (core, k + 1);
668 avr_core_inst_CKS_set (core, 2);
669 }
670 else
671 {
672 avr_core_PC_incr (core, 1);
673 avr_core_inst_CKS_set (core, 1);
674 }
675
676 return opcode_BRBC;
677 }
678
679 static int
680 avr_op_BRBS (AvrCore *core, uint16_t opcode, unsigned int arg1,
681 unsigned int arg2)
682 {
683 /*
684 * Branch if Status Flag Set.
685 *
686 * Pass control directly to the specific bit operation.
687 *
688 * Opcode : 1111 00kk kkkk ksss
689 * Usage : BRBS s, k
690 * Operation : if (SREG(s) = 1) then PC <- PC + k + 1
691 * Flags : None
692 * Num Clocks : 1 / 2
693 *
694 * k is an relative address represented in two's complements.
695 * (64 < k <= 64)
696 */
697 int bit = arg1;
698 int k = arg2;
699
700 if (avr_core_sreg_get_bit (core, bit) != 0)
701 {
702 avr_core_PC_incr (core, k + 1);
703 avr_core_inst_CKS_set (core, 2);
704 }
705 else
706 {
707 avr_core_PC_incr (core, 1);
708 avr_core_inst_CKS_set (core, 1);
709 }
710
711 return opcode_BRBS;
712 }
713
714 static int
715 avr_op_BREAK (AvrCore *core, uint16_t opcode, unsigned int arg1,
716 unsigned int arg2)
717 {
718 /*
719 * The BREAK instruction only available on devices with JTAG support. We
720 * use it to implement break points for all devices though. When the
721 * debugger sets a break point we will replace the insn at the requested
722 * PC with the BREAK insn and save the PC and original insn on the break
723 * point list. Thus, we only need to walk the break point list when we
724 * reach a break insn.
725 *
726 * When a break occurs, we will return control to the caller _without_
727 * incrementing PC as the insn set datasheet says.
728 *
729 * Opcode : 1001 0101 1001 1000
730 * Usage : BREAK
731 * Operation : Puts the in Stopped Mode if supported, NOP otherwise.
732 * Flags : None
733 * Num Clocks : 1
734 */
735
736 avr_message ("BREAK POINT: PC = 0x%08x: clock = %lld\n",
737 avr_core_PC_get (core), avr_core_CK_get (core));
738
739 /* FIXME: TRoth/2002-10-15: Should we execute the original insn which the
740 break replaced here or let the caller handle that? For now we defer
741 that to the caller. */
742
743 /* return opcode_BREAK; */
744 return BREAK_POINT;
745 }
746
747 static int
748 avr_op_BSET (AvrCore *core, uint16_t opcode, unsigned int arg1,
749 unsigned int arg2)
750 {
751 /*
752 * Set a single flag or bit in SREG.
753 *
754 * Opcode : 1001 0100 0sss 1000
755 * Usage : BSET
756 * Operation : SREG(s) <- 1
757 * Flags : SREG(s)
758 * Num Clocks : 1
759 */
760 avr_core_sreg_set_bit (core, arg1, 1);
761 avr_core_PC_incr (core, 1);
762 avr_core_inst_CKS_set (core, 1);
763
764 return opcode_BSET;
765 }
766
767 static int
768 avr_op_BST (AvrCore *core, uint16_t opcode, unsigned int arg1,
769 unsigned int arg2)
770 {
771 /*
772 * Bit Store from Register to T.
773 *
774 * Opcode : 1111 101d dddd 0bbb
775 * Usage : BST Rd, b
776 * Operation : T <- Rd(b)
777 * Flags : T
778 * Num Clocks : 1
779 */
780 int Rd = arg1;
781 int bit = arg2;
782
783 uint8_t rd = avr_core_gpwr_get (core, Rd);
784 avr_core_sreg_set_bit (core, SREG_T, (rd >> bit) & 0x1);
785
786 avr_core_PC_incr (core, 1);
787 avr_core_inst_CKS_set (core, 1);
788
789 return opcode_BST;
790 }
791
792 static int
793 avr_op_CALL (AvrCore *core, uint16_t opcode, unsigned int arg1,
794 unsigned int arg2)
795 {
796 /*
797 * Call Subroutine.
798 *
799 * Opcode : 1001 010k kkkk 111k kkkk kkkk kkkk kkkk
800 * Usage : CALL k
801 * Operation : PC <- k
802 * Flags : None
803 * Num Clocks : 4 / 5
804 */
805 int pc = avr_core_PC_get (core);
806 int pc_bytes = avr_core_PC_size (core);
807
808 int kh = arg1;
809 int kl = flash_read (core->flash, pc + 1);
810
811 int k = (kh << 16) + kl;
812
813 if ((pc_bytes == 2) && (k > 0xffff))
814 avr_error ("Address out of allowed range: 0x%06x", k);
815
816 avr_core_stack_push (core, pc_bytes, pc + 2);
817
818 avr_core_PC_set (core, k);
819 avr_core_inst_CKS_set (core, pc_bytes + 2);
820
821 return opcode_CALL;
822 }
823
824 static int
825 avr_op_CBI (AvrCore *core, uint16_t opcode, unsigned int arg1,
826 unsigned int arg2)
827 {
828 /*
829 * Clear Bit in I/O Register.
830 *
831 * Opcode : 1001 1000 AAAA Abbb
832 * Usage : CBI A, b
833 * Operation : I/O(A, b) <- 0
834 * Flags : None
835 * Num Clocks : 2
836 */
837 int A = arg1;
838 int b = arg2;
839
840 uint8_t val = avr_core_io_read (core, A);
841 avr_core_io_write (core, A, val & ~(1 << b));
842
843 avr_core_PC_incr (core, 1);
844 avr_core_inst_CKS_set (core, 2);
845
846 return opcode_CBI;
847 }
848
849 static int
850 avr_op_COM (AvrCore *core, uint16_t opcode, unsigned int arg1,
851 unsigned int arg2)
852 {
853 /*
854 * One's Complement.
855 *
856 * Opcode : 1001 010d dddd 0000
857 * Usage : COM Rd
858 * Operation : Rd <- $FF - Rd
859 * Flags : Z,C,N,V,S
860 * Num Clocks : 1
861 */
862 int Z, C, N, V, S;
863
864 int Rd = arg1;
865
866 uint8_t rd = avr_core_gpwr_get (core, Rd);
867 uint8_t res = 0xff - rd;
868
869 uint8_t sreg = avr_core_sreg_get (core);
870
871 sreg = set_bit_in_byte (sreg, SREG_N, N = ((res >> 7) & 0x1));
872 sreg = set_bit_in_byte (sreg, SREG_C, C = 1);
873 sreg = set_bit_in_byte (sreg, SREG_V, V = 0);
874 sreg = set_bit_in_byte (sreg, SREG_S, S = (N ^ V));
875 sreg = set_bit_in_byte (sreg, SREG_Z, Z = ((res & 0xff) == 0));
876
877 avr_core_sreg_set (core, sreg);
878
879 avr_core_gpwr_set (core, Rd, res);
880 avr_core_PC_incr (core, 1);
881 avr_core_inst_CKS_set (core, 1);
882
883 return opcode_COM;
884 }
885
886 static int
887 avr_op_CP (AvrCore *core, uint16_t opcode, unsigned int arg1,
888 unsigned int arg2)
889 {
890 /*
891 * Compare.
892 *
893 * Opcode : 0001 01rd dddd rrrr
894 * Usage : CP Rd, Rr
895 * Operation : Rd - Rr
896 * Flags : Z,C,N,V,S,H
897 * Num Clocks : 1
898 */
899 int Z, C, N, V, S, H;
900
901 int Rd = arg1;
902 int Rr = arg2;
903
904 uint8_t rd = avr_core_gpwr_get (core, Rd);
905 uint8_t rr = avr_core_gpwr_get (core, Rr);
906 uint8_t res = rd - rr;
907
908 uint8_t sreg = avr_core_sreg_get (core);
909
910 sreg = set_bit_in_byte (sreg, SREG_H, H =
911 get_compare_carry (res, rd, rr, 3));
912 sreg = set_bit_in_byte (sreg, SREG_V, V =
913 get_compare_overflow (res, rd, rr));
914 sreg = set_bit_in_byte (sreg, SREG_N, N = ((res >> 7) & 0x1));
915 sreg = set_bit_in_byte (sreg, SREG_S, S = (N ^ V));
916 sreg = set_bit_in_byte (sreg, SREG_Z, Z = ((res & 0xff) == 0));
917 sreg = set_bit_in_byte (sreg, SREG_C, C =
918 get_compare_carry (res, rd, rr, 7));
919
920 avr_core_sreg_set (core, sreg);
921
922 avr_core_PC_incr (core, 1);
923 avr_core_inst_CKS_set (core, 1);
924
925 return opcode_CP;
926 }
927
928 static int
929 avr_op_CPC (AvrCore *core, uint16_t opcode, unsigned int arg1,
930 unsigned int arg2)
931 {
932 /*
933 * Compare with Carry.
934 *
935 * Opcode : 0000 01rd dddd rrrr
936 * Usage : CPC Rd, Rr
937 * Operation : Rd - Rr - C
938 * Flags : Z,C,N,V,S,H
939 * Num Clocks : 1
940 */
941 int Z, C, N, V, S, H, prev_Z;
942
943 int Rd = arg1;
944 int Rr = arg2;
945
946 uint8_t rd = avr_core_gpwr_get (core, Rd);
947 uint8_t rr = avr_core_gpwr_get (core, Rr);
948 uint8_t res = rd - rr - avr_core_sreg_get_bit (core, SREG_C);
949
950 uint8_t sreg = avr_core_sreg_get (core);
951
952 sreg = set_bit_in_byte (sreg, SREG_H, H =
953 get_compare_carry (res, rd, rr, 3));
954 sreg = set_bit_in_byte (sreg, SREG_V, V =
955 get_compare_overflow (res, rd, rr));
956 sreg = set_bit_in_byte (sreg, SREG_N, N = ((res >> 7) & 0x1));
957 sreg = set_bit_in_byte (sreg, SREG_S, S = (N ^ V));
958 sreg = set_bit_in_byte (sreg, SREG_C, C =
959 get_compare_carry (res, rd, rr, 7));
960
961 /* Previous value remains unchanged when result is 0; cleared otherwise */
962 Z = ((res & 0xff) == 0);
963 prev_Z = avr_core_sreg_get_bit (core, SREG_Z);
964 sreg = set_bit_in_byte (sreg, SREG_Z, Z && prev_Z);
965
966 avr_core_sreg_set (core, sreg);
967
968 avr_core_PC_incr (core, 1);
969 avr_core_inst_CKS_set (core, 1);
970
971 return opcode_CPC;
972 }
973
974 static int
975 avr_op_CPI (AvrCore *core, uint16_t opcode, unsigned int arg1,
976 unsigned int arg2)
977 {
978 /*
979 * Compare with Immediate.
980 *
981 * Opcode : 0011 KKKK dddd KKKK
982 * Usage : CPI Rd, K
983 * Operation : Rd - K
984 * Flags : Z,C,N,V,S,H
985 * Num Clocks : 1
986 */
987 int Z, C, N, V, S, H;
988
989 int Rd = arg1;
990 uint8_t K = arg2;
991
992 uint8_t rd = avr_core_gpwr_get (core, Rd);
993 uint8_t res = rd - K;
994
995 uint8_t sreg = avr_core_sreg_get (core);
996
997 sreg = set_bit_in_byte (sreg, SREG_H, H =
998 get_compare_carry (res, rd, K, 3));
999 sreg = set_bit_in_byte (sreg, SREG_V, V =
1000 get_compare_overflow (res, rd, K));
1001 sreg = set_bit_in_byte (sreg, SREG_N, N = ((res >> 7) & 0x1));
1002 sreg = set_bit_in_byte (sreg, SREG_S, S = (N ^ V));
1003 sreg = set_bit_in_byte (sreg, SREG_Z, Z = ((res & 0xff) == 0));
1004 sreg = set_bit_in_byte (sreg, SREG_C, C =
1005 get_compare_carry (res, rd, K, 7));
1006
1007 avr_core_sreg_set (core, sreg);
1008
1009 avr_core_PC_incr (core, 1);
1010 avr_core_inst_CKS_set (core, 1);
1011
1012 return opcode_CPI;
1013 }
1014
1015 static int
1016 avr_op_CPSE (AvrCore *core, uint16_t opcode, unsigned int arg1,
1017 unsigned int arg2)
1018 {
1019 /*
1020 * Compare, Skip if Equal.
1021 *
1022 * Opcode : 0001 00rd dddd rrrr
1023 * Usage : CPSE Rd, Rr
1024 * Operation : if (Rd = Rr) PC <- PC + 2 or 3
1025 * Flags : None
1026 * Num Clocks : 1 / 2 / 3
1027 */
1028 int skip;
1029
1030 int Rd = arg1;
1031 int Rr = arg2;
1032
1033 uint8_t rd = avr_core_gpwr_get (core, Rd);
1034 uint8_t rr = avr_core_gpwr_get (core, Rr);
1035
1036 if (is_next_inst_2_words (core))
1037 skip = 3;
1038 else
1039 skip = 2;
1040
1041 if (rd == rr)
1042 {
1043 avr_core_PC_incr (core, skip);
1044 avr_core_inst_CKS_set (core, skip);
1045 }
1046 else
1047 {
1048 avr_core_PC_incr (core, 1);
1049 avr_core_inst_CKS_set (core, 1);
1050 }
1051
1052 return opcode_CPSE;
1053 }
1054
1055 static int
1056 avr_op_DEC (AvrCore *core, uint16_t opcode, unsigned int arg1,
1057 unsigned int arg2)
1058 {
1059 /*
1060 * Decrement.
1061 *
1062 * Opcode : 1001 010d dddd 1010
1063 * Usage : DEC Rd
1064 * Operation : Rd <- Rd - 1
1065 * Flags : Z,N,V,S
1066 * Num Clocks : 1
1067 */
1068 int Z, N, V, S;
1069
1070 int Rd = arg1;
1071 uint8_t rd = avr_core_gpwr_get (core, Rd);
1072 uint8_t res = rd - 1;
1073
1074 uint8_t sreg = avr_core_sreg_get (core);
1075
1076 sreg = set_bit_in_byte (sreg, SREG_N, N = ((res >> 7) & 0x1));
1077 sreg = set_bit_in_byte (sreg, SREG_V, V = (rd == 0x80));
1078 sreg = set_bit_in_byte (sreg, SREG_S, S = (N ^ V));
1079 sreg = set_bit_in_byte (sreg, SREG_Z, Z = ((res & 0xff) == 0));
1080
1081 avr_core_sreg_set (core, sreg);
1082
1083 avr_core_gpwr_set (core, Rd, res);
1084
1085 avr_core_PC_incr (core, 1);
1086 avr_core_inst_CKS_set (core, 1);
1087
1088 return opcode_DEC;
1089 }
1090
1091 static int
1092 avr_op_EICALL (AvrCore *core, uint16_t opcode, unsigned int arg1,
1093 unsigned int arg2)
1094 {
1095 /*
1096 * Extended Indirect Call to (Z).
1097 *
1098 * Opcode : 1001 0101 0001 1001
1099 * Usage : EICALL
1100 * Operation : PC(15:0) <- Z, PC(21:16) <- EIND
1101 * Flags : None
1102 * Num Clocks : 4
1103 */
1104 int pc = avr_core_PC_get (core);
1105 int pc_bytes = 3;
1106
1107 /* Z is R31:R30 */
1108 int new_pc =
1109 ((core->EIND & 0x3f) << 16) + (avr_core_gpwr_get (core, 31) << 8) +
1110 avr_core_gpwr_get (core, 30);
1111
1112 avr_warning ("needs serious code review\n");
1113
1114 avr_core_stack_push (core, pc_bytes, pc + 1);
1115
1116 avr_core_PC_set (core, new_pc);
1117 avr_core_inst_CKS_set (core, 4);
1118
1119 return opcode_EICALL;
1120 }
1121
1122 static int
1123 avr_op_EIJMP (AvrCore *core, uint16_t opcode, unsigned int arg1,
1124 unsigned int arg2)
1125 {
1126 /*
1127 * Extended Indirect Jmp to (Z).
1128 *
1129 * Opcode : 1001 0100 0001 1001
1130 * Usage : EIJMP
1131 * Operation : PC(15:0) <- Z, PC(21:16) <- EIND
1132 * Flags : None
1133 * Num Clocks : 2
1134 */
1135
1136 /* Z is R31:R30 */
1137 int new_pc =
1138 ((core->EIND & 0x3f) << 16) + (avr_core_gpwr_get (core, 31) << 8) +
1139 avr_core_gpwr_get (core, 30);
1140
1141 avr_warning ("needs serious code review\n");
1142
1143 avr_core_PC_set (core, new_pc);
1144 avr_core_inst_CKS_set (core, 2);
1145
1146 return opcode_EIJMP;
1147 }
1148
1149 static int
1150 avr_op_ELPM_Z (AvrCore *core, uint16_t opcode, unsigned int arg1,
1151 unsigned int arg2)
1152 {
1153 /*
1154 * Extended Load Program Memory.
1155 *
1156 * Opcode : 1001 000d dddd 0110
1157 * Usage : ELPM Rd, Z
1158 * Operation : R <- (RAMPZ:Z)
1159 * Flags : None
1160 * Num Clocks : 3
1161 */
1162 int Z, high_byte, flash_addr;
1163 uint16_t data;
1164
1165 int Rd = arg1;
1166
1167 if ((Rd == 30) || (Rd == 31))
1168 avr_error ("Results of operation are undefined");
1169
1170 avr_warning ("needs serious code review\n");
1171
1172 /* FIXME: Is this correct? */
1173 /* Z is R31:R30 */
1174 Z = ((avr_core_rampz_get (core) & 0x3f) << 16) +
1175 (avr_core_gpwr_get (core, 31) << 8) + avr_core_gpwr_get (core, 30);
1176
1177 high_byte = Z & 0x1;
1178
1179 flash_addr = Z / 2;
1180
1181 data = flash_read (core->flash, flash_addr);
1182
1183 if (high_byte == 1)
1184 avr_core_gpwr_set (core, Rd, data >> 8);
1185 else
1186 avr_core_gpwr_set (core, Rd, data & 0xff);
1187
1188 avr_core_PC_incr (core, 1);
1189 avr_core_inst_CKS_set (core, 3);
1190
1191 return opcode_ELPM_Z;
1192 }
1193
1194 static int
1195 avr_op_ELPM_Z_incr (AvrCore *core, uint16_t opcode, unsigned int arg1,
1196 unsigned int arg2)
1197 {
1198 /*
1199 * Extended Ld Prg Mem and Post-Incr.
1200 *
1201 * Opcode : 1001 000d dddd 0111
1202 * Usage : ELPM Rd, Z+
1203 * Operation : Rd <- (RAMPZ:Z), Z <- Z + 1
1204 * Flags : None
1205 * Num Clocks : 3
1206 */
1207 int Z, high_byte, flash_addr;
1208 uint16_t data;
1209
1210 int Rd = arg1;
1211
1212 if ((Rd == 30) || (Rd == 31))
1213 avr_error ("Results of operation are undefined");
1214
1215 /* TRoth/2002-08-14: This seems to work ok for me. */
1216 /* avr_warning( "needs serious code review\n" ); */
1217
1218 /* FIXME: Is this correct? */
1219 /* Z is R31:R30 */
1220 Z = ((avr_core_rampz_get (core) & 0x3f) << 16) +
1221 (avr_core_gpwr_get (core, 31) << 8) + avr_core_gpwr_get (core, 30);
1222
1223 high_byte = Z & 0x1;
1224
1225 flash_addr = Z / 2;
1226
1227 data = flash_read (core->flash, flash_addr);
1228
1229 if (high_byte == 1)
1230 avr_core_gpwr_set (core, Rd, data >> 8);
1231 else
1232 avr_core_gpwr_set (core, Rd, data & 0xff);
1233
1234 /* post increment Z */
1235 Z += 1;
1236 avr_core_gpwr_set (core, 30, Z & 0xff);
1237 avr_core_gpwr_set (core, 31, Z >> 8);
1238 avr_core_rampz_set (core, (Z >> 16) & 0x3f);
1239
1240 avr_core_PC_incr (core, 1);
1241 avr_core_inst_CKS_set (core, 3);
1242
1243 return opcode_ELPM_Z_incr;
1244 }
1245
1246 static int
1247 avr_op_ELPM (AvrCore *core, uint16_t opcode, unsigned int arg1,
1248 unsigned int arg2)
1249 {
1250 /*
1251 * Extended Load Program Memory.
1252 *
1253 * This is the same as avr_op_ELPM_Z with Rd = R0.
1254 *
1255 * Opcode : 1001 0101 1101 1000
1256 * Usage : ELPM
1257 * Operation : R0 <- (RAMPZ:Z)
1258 * Flags : None
1259 * Num Clocks : 3
1260 */
1261 avr_op_ELPM_Z (core, 0x9006, arg1, arg2);
1262 return opcode_ELPM;
1263 }
1264
1265 static int
1266 avr_op_EOR (AvrCore *core, uint16_t opcode, unsigned int arg1,
1267 unsigned int arg2)
1268 {
1269 /*
1270 * Exclusive OR.
1271 *
1272 * Opcode : 0010 01rd dddd rrrr
1273 * Usage : EOR Rd, Rr
1274 * Operation : Rd <- Rd ^ Rr
1275 * Flags : Z,N,V,S
1276 * Num Clocks : 1
1277 */
1278 int Z, N, V, S;
1279
1280 int Rd = arg1;
1281 int Rr = arg2;
1282
1283 uint8_t rd = avr_core_gpwr_get (core, Rd);
1284 uint8_t rr = avr_core_gpwr_get (core, Rr);
1285
1286 uint8_t res = rd ^ rr;
1287
1288 uint8_t sreg = avr_core_sreg_get (core);
1289
1290 sreg = set_bit_in_byte (sreg, SREG_V, V = 0);
1291 sreg = set_bit_in_byte (sreg, SREG_N, N = ((res >> 7) & 0x1));
1292 sreg = set_bit_in_byte (sreg, SREG_S, S = (N ^ V));
1293 sreg = set_bit_in_byte (sreg, SREG_Z, Z = ((res & 0xff) == 0));
1294
1295 avr_core_sreg_set (core, sreg);
1296
1297 avr_core_gpwr_set (core, Rd, res);
1298
1299 avr_core_PC_incr (core, 1);
1300 avr_core_inst_CKS_set (core, 1);
1301
1302 return opcode_EOR;
1303 }
1304
1305 static int
1306 avr_op_ESPM (AvrCore *core, uint16_t opcode, unsigned int arg1,
1307 unsigned int arg2)
1308 {
1309 /*
1310 * Extended Store Program Memory.
1311 *
1312 * Opcode : 1001 0101 1111 1000
1313 * Usage : ESPM
1314 * Operation : (RAMPZ:Z) <- R1:R0
1315 * Flags : None
1316 * Num Clocks : -
1317 */
1318 avr_error ("This opcode is not implemented yet: 0x%04x", opcode);
1319 return opcode_ESPM;
1320 }
1321
1322 /**
1323 ** I don't know how this Fractional Multiplication works.
1324 ** If someone wishes to enlighten me, I write these.
1325 **/
1326
1327 static int
1328 avr_op_FMUL (AvrCore *core, uint16_t opcode, unsigned int arg1,
1329 unsigned int arg2)
1330 {
1331 /*
1332 * Fractional Mult Unsigned.
1333 *
1334 * Opcode : 0000 0011 0ddd 1rrr
1335 * Usage : FMUL Rd, Rr
1336 * Operation : R1:R0 <- (Rd * Rr)<<1 (UU)
1337 * Flags : Z,C
1338 * Num Clocks : 2
1339 */
1340 int Rd = arg1;
1341 int Rr = arg2;
1342
1343 uint8_t rd = avr_core_gpwr_get (core, Rd);
1344 uint8_t rr = avr_core_gpwr_get (core, Rr);
1345
1346 uint16_t resp = rd * rr;
1347 uint16_t res = resp << 1;
1348
1349 uint8_t sreg = avr_core_sreg_get (core);
1350
1351 sreg = set_bit_in_byte (sreg, SREG_Z, ((res & 0xffff) == 0));
1352 sreg = set_bit_in_byte (sreg, SREG_C, ((resp >> 15) & 0x1));
1353
1354 avr_core_sreg_set (core, sreg);
1355
1356 /* result goes in R1:R0 */
1357 avr_core_gpwr_set (core, 1, res >> 8);
1358 avr_core_gpwr_set (core, 0, res & 0xff);
1359
1360 avr_core_PC_incr (core, 1);
1361 avr_core_inst_CKS_set (core, 2);
1362
1363 return opcode_FMUL;
1364 }
1365
1366 static int
1367 avr_op_FMULS (AvrCore *core, uint16_t opcode, unsigned int arg1,
1368 unsigned int arg2)
1369 {
1370 /*
1371 * Fractional Mult Signed.
1372 *
1373 * Opcode : 0000 0011 1ddd 0rrr
1374 * Usage : FMULS Rd, Rr
1375 * Operation : R1:R0 <- (Rd * Rr)<<1 (SS)
1376 * Flags : Z,C
1377 * Num Clocks : 2
1378 */
1379 int Rd = arg1;
1380 int Rr = arg2;
1381
1382 int8_t rd = avr_core_gpwr_get (core, Rd);
1383 int8_t rr = avr_core_gpwr_get (core, Rr);
1384
1385 uint16_t resp = rd * rr;
1386 uint16_t res = resp << 1;
1387
1388 uint8_t sreg = avr_core_sreg_get (core);
1389
1390 sreg = set_bit_in_byte (sreg, SREG_Z, ((res & 0xffff) == 0));
1391 sreg = set_bit_in_byte (sreg, SREG_C, ((resp >> 15) & 0x1));
1392
1393 avr_core_sreg_set (core, sreg);
1394
1395 /* result goes in R1:R0 */
1396 avr_core_gpwr_set (core, 1, res >> 8);
1397 avr_core_gpwr_set (core, 0, res & 0xff);
1398
1399 avr_core_PC_incr (core, 1);
1400 avr_core_inst_CKS_set (core, 2);
1401
1402 return opcode_FMULS;
1403 }
1404
1405 static int
1406 avr_op_FMULSU (AvrCore *core, uint16_t opcode, unsigned int arg1,
1407 unsigned int arg2)
1408 {
1409 /*
1410 * Fract Mult Signed w/ Unsigned.
1411 *
1412 * Opcode : 0000 0011 1ddd 1rrr
1413 * Usage : FMULSU Rd, Rr
1414 * Operation : R1:R0 <- (Rd * Rr)<<1 (SU)
1415 * Flags : Z,C
1416 * Num Clocks : 2
1417 */
1418 int Rd = arg1;
1419 int Rr = arg2;
1420
1421 int8_t rd = avr_core_gpwr_get (core, Rd);
1422 uint8_t rr = avr_core_gpwr_get (core, Rr);
1423
1424 uint16_t resp = rd * rr;
1425 uint16_t res = resp << 1;
1426
1427 uint8_t sreg = avr_core_sreg_get (core);
1428
1429 sreg = set_bit_in_byte (sreg, SREG_Z, ((res & 0xffff) == 0));
1430 sreg = set_bit_in_byte (sreg, SREG_C, ((resp >> 15) & 0x1));
1431
1432 avr_core_sreg_set (core, sreg);
1433
1434 /* result goes in R1:R0 */
1435 avr_core_gpwr_set (core, 1, res >> 8);
1436 avr_core_gpwr_set (core, 0, res & 0xff);
1437
1438 avr_core_PC_incr (core, 1);
1439 avr_core_inst_CKS_set (core, 2);
1440
1441 return opcode_FMULSU;
1442 }
1443
1444 static int
1445 avr_op_ICALL (AvrCore *core, uint16_t opcode, unsigned int arg1,
1446 unsigned int arg2)
1447 {
1448 /*
1449 * Indirect Call to (Z).
1450 *
1451 * Opcode : 1001 0101 0000 1001
1452 * Usage : ICALL
1453 * Operation : PC(15:0) <- Z, PC(21:16) <- 0
1454 * Flags : None
1455 * Num Clocks : 3 / 4
1456 */
1457 int pc = avr_core_PC_get (core);
1458 int pc_bytes = avr_core_PC_size (core);
1459
1460 /* Z is R31:R30 */
1461 int new_pc =
1462 (avr_core_gpwr_get (core, 31) << 8) + avr_core_gpwr_get (core, 30);
1463
1464 avr_core_stack_push (core, pc_bytes, pc + 1);
1465
1466 avr_core_PC_set (core, new_pc);
1467 avr_core_inst_CKS_set (core, pc_bytes + 1);
1468
1469 return opcode_ICALL;
1470 }
1471
1472 static int
1473 avr_op_IJMP (AvrCore *core, uint16_t opcode, unsigned int arg1,
1474 unsigned int arg2)
1475 {
1476 /*
1477 * Indirect Jump to (Z).
1478 *
1479 * Opcode : 1001 0100 0000 1001
1480 * Usage : IJMP
1481 * Operation : PC(15:0) <- Z, PC(21:16) <- 0
1482 * Flags : None
1483 * Num Clocks : 2
1484 */
1485
1486 /* Z is R31:R30 */
1487 int new_pc =
1488 (avr_core_gpwr_get (core, 31) << 8) + avr_core_gpwr_get (core, 30);
1489 avr_core_PC_set (core, new_pc);
1490 avr_core_inst_CKS_set (core, 2);
1491
1492 return opcode_IJMP;
1493 }
1494
1495 static int
1496 avr_op_IN (AvrCore *core, uint16_t opcode, unsigned int arg1,
1497 unsigned int arg2)
1498 {
1499 /*
1500 * In From I/O Location.
1501 *
1502 * Opcode : 1011 0AAd dddd AAAA
1503 * Usage : IN Rd, A
1504 * Operation : Rd <- I/O(A)
1505 * Flags : None
1506 * Num Clocks : 1
1507 */
1508 int Rd = arg1;
1509 int A = arg2;
1510
1511 avr_core_gpwr_set (core, Rd, avr_core_io_read (core, A));
1512
1513 avr_core_PC_incr (core, 1);
1514 avr_core_inst_CKS_set (core, 1);
1515
1516 return opcode_IN;
1517 }
1518
1519 static int
1520 avr_op_INC (AvrCore *core, uint16_t opcode, unsigned int arg1,
1521 unsigned int arg2)
1522 {
1523 /*
1524 * Increment.
1525 *
1526 * Opcode : 1001 010d dddd 0011
1527 * Usage : INC Rd
1528 * Operation : Rd <- Rd + 1
1529 * Flags : Z,N,V,S
1530 * Num Clocks : 1
1531 */
1532 int Z, N, V, S;
1533
1534 int Rd = arg1;
1535 uint8_t rd = avr_core_gpwr_get (core, Rd);
1536 uint8_t res = rd + 1;
1537
1538 uint8_t sreg = avr_core_sreg_get (core);
1539
1540 sreg = set_bit_in_byte (sreg, SREG_N, N = ((res >> 7) & 0x1));
1541 sreg = set_bit_in_byte (sreg, SREG_V, V = (rd == 0x7f));
1542 sreg = set_bit_in_byte (sreg, SREG_S, S = (N ^ V));
1543 sreg = set_bit_in_byte (sreg, SREG_Z, Z = ((res & 0xff) == 0));
1544
1545 avr_core_sreg_set (core, sreg);
1546
1547 avr_core_gpwr_set (core, Rd, res);
1548
1549 avr_core_PC_incr (core, 1);
1550 avr_core_inst_CKS_set (core, 1);
1551
1552 return opcode_INC;
1553 }
1554
1555 static int
1556 avr_op_JMP (AvrCore *core, uint16_t opcode, unsigned int arg1,
1557 unsigned int arg2)
1558 {
1559 /*
1560 * Jump.
1561 *
1562 * Opcode : 1001 010k kkkk 110k kkkk kkkk kkkk kkkk
1563 * Usage : JMP k
1564 * Operation : PC <- k
1565 * Flags : None
1566 * Num Clocks : 3
1567 */
1568 int kh = arg1;
1569 int kl = flash_read (core->flash, avr_core_PC_get (core) + 1);
1570
1571 int k = (kh << 16) + kl;
1572
1573 avr_core_PC_set (core, k);
1574 avr_core_inst_CKS_set (core, 3);
1575
1576 return opcode_JMP;
1577 }
1578
1579 static int
1580 avr_op_LDD_Y (AvrCore *core, uint16_t opcode, unsigned int arg1,
1581 unsigned int arg2)
1582 {
1583 /*
1584 * Load Indirect with Displacement using index Y.
1585 *
1586 * Opcode : 10q0 qq0d dddd 1qqq
1587 * Usage : LDD Rd, Y+q
1588 * Operation : Rd <- (Y + q)
1589 * Flags : None
1590 * Num Clocks : 2
1591 */
1592 uint16_t Y;
1593 int Rd = arg1;
1594 int q = arg2;
1595
1596 /* Y is R29:R28 */
1597 Y = (avr_core_gpwr_get (core, 29) << 8) + avr_core_gpwr_get (core, 28);
1598
1599 avr_core_gpwr_set (core, Rd, avr_core_mem_read (core, Y + q));
1600
1601 avr_core_PC_incr (core, 1);
1602 avr_core_inst_CKS_set (core, 2);
1603
1604 return opcode_LDD_Y;
1605 }
1606
1607 static int
1608 avr_op_LDD_Z (AvrCore *core, uint16_t opcode, unsigned int arg1,
1609 unsigned int arg2)
1610 {
1611 /*
1612 * Load Indirect with Displacement using index Z.
1613 *
1614 * Opcode : 10q0 qq0d dddd 0qqq
1615 * Usage : LDD Rd, Z+q
1616 * Operation : Rd <- (Z + q)
1617 * Flags : None
1618 * Num Clocks : 2
1619 */
1620 uint16_t Z;
1621
1622 int Rd = arg1;
1623 int q = arg2;
1624
1625 /* Z is R31:R30 */
1626 Z = (avr_core_gpwr_get (core, 31) << 8) + avr_core_gpwr_get (core, 30);
1627
1628 avr_core_gpwr_set (core, Rd, avr_core_mem_read (core, Z + q));
1629
1630 avr_core_PC_incr (core, 1);
1631 avr_core_inst_CKS_set (core, 2);
1632
1633 return opcode_LDD_Z;
1634 }
1635
1636 static int
1637 avr_op_LDI (AvrCore *core, uint16_t opcode, unsigned int arg1,
1638 unsigned int arg2)
1639 {
1640 /*
1641 * Load Immediate.
1642 *
1643 * Opcode : 1110 KKKK dddd KKKK
1644 * Usage : LDI Rd, K
1645 * Operation : Rd <- K
1646 * Flags : None
1647 * Num Clocks : 1
1648 */
1649 int Rd = arg1;
1650 uint8_t K = arg2;
1651
1652 avr_core_gpwr_set (core, Rd, K);
1653
1654 avr_core_PC_incr (core, 1);
1655 avr_core_inst_CKS_set (core, 1);
1656
1657 return opcode_LDI;
1658 }
1659
1660 static int
1661 avr_op_LDS (AvrCore *core, uint16_t opcode, unsigned int arg1,
1662 unsigned int arg2)
1663 {
1664 /*
1665 * Load Direct from data space.
1666 *
1667 * Opcode : 1001 000d dddd 0000 kkkk kkkk kkkk kkkk
1668 * Usage : LDS Rd, k
1669 * Operation : Rd <- (k)
1670 * Flags : None
1671 * Num Clocks : 2
1672 */
1673 int Rd = arg1;
1674
1675 /* Get data at k in current data segment and put into Rd */
1676 int k_pc = avr_core_PC_get (core) + 1;
1677 int k = flash_read (core->flash, k_pc);
1678
1679 avr_core_gpwr_set (core, Rd, avr_core_mem_read (core, k));
1680
1681 avr_core_PC_incr (core, 2);
1682 avr_core_inst_CKS_set (core, 2);
1683
1684 return opcode_LDS;
1685 }
1686
1687 static int
1688 avr_op_LD_X (AvrCore *core, uint16_t opcode, unsigned int arg1,
1689 unsigned int arg2)
1690 {
1691 /*
1692 * Load Indirect using index X.
1693 *
1694 * Opcode : 1001 000d dddd 1100
1695 * Usage : LD Rd, X
1696 * Operation : Rd <- (X)
1697 * Flags : None
1698 * Num Clocks : 2
1699 */
1700 uint16_t X;
1701
1702 int Rd = arg1;
1703
1704 /* X is R27:R26 */
1705 X = (avr_core_gpwr_get (core, 27) << 8) + avr_core_gpwr_get (core, 26);
1706
1707 avr_core_gpwr_set (core, Rd, avr_core_mem_read (core, X));
1708
1709 avr_core_PC_incr (core, 1);
1710 avr_core_inst_CKS_set (core, 2);
1711
1712 return opcode_LD_X;
1713 }
1714
1715 static int
1716 avr_op_LD_X_decr (AvrCore *core, uint16_t opcode, unsigned int arg1,
1717 unsigned int arg2)
1718 {
1719 /*
1720 * Load Indirect and Pre-Decrement using index X.
1721 *
1722 * Opcode : 1001 000d dddd 1110
1723 * Usage : LD Rd, -X
1724 * Operation : X <- X - 1, Rd <- (X)
1725 * Flags : None
1726 * Num Clocks : 2
1727 */
1728 uint16_t X;
1729
1730 int Rd = arg1;
1731
1732 if ((Rd == 26) || (Rd == 27))
1733 avr_error ("Results of operation are undefined");
1734
1735 /* X is R27:R26 */
1736 X = (avr_core_gpwr_get (core, 27) << 8) + avr_core_gpwr_get (core, 26);
1737
1738 /* Perform pre-decrement */
1739 X -= 1;
1740 avr_core_gpwr_set (core, 26, X & 0xff);
1741 avr_core_gpwr_set (core, 27, X >> 8);
1742
1743 avr_core_gpwr_set (core, Rd, avr_core_mem_read (core, X));
1744
1745 avr_core_PC_incr (core, 1);
1746 avr_core_inst_CKS_set (core, 2);
1747
1748 return opcode_LD_X_decr;
1749 }
1750
1751 static int
1752 avr_op_LD_X_incr (AvrCore *core, uint16_t opcode, unsigned int arg1,
1753 unsigned int arg2)
1754 {
1755 /*
1756 * Load Indirect and Post-Increment using index X.
1757 *
1758 * Opcode : 1001 000d dddd 1101
1759 * Usage : LD Rd, X+
1760 * Operation : Rd <- (X), X <- X + 1
1761 * Flags : None
1762 * Num Clocks : 2
1763 */
1764 uint16_t X;
1765
1766 int Rd = arg1;
1767
1768 if ((Rd == 26) || (Rd == 27))
1769 avr_error ("Results of operation are undefined");
1770
1771 /* X is R27:R26 */
1772 X = (avr_core_gpwr_get (core, 27) << 8) + avr_core_gpwr_get (core, 26);
1773
1774 avr_core_gpwr_set (core, Rd, avr_core_mem_read (core, X));
1775
1776 /* Perform post-increment */
1777 X += 1;
1778 avr_core_gpwr_set (core, 26, X & 0xff);
1779 avr_core_gpwr_set (core, 27, X >> 8);
1780
1781 avr_core_PC_incr (core, 1);
1782 avr_core_inst_CKS_set (core, 2);
1783
1784 return opcode_LD_X_incr;
1785 }
1786
1787 static int
1788 avr_op_LD_Y_decr (AvrCore *core, uint16_t opcode, unsigned int arg1,
1789 unsigned int arg2)
1790 {
1791 /*
1792 * Load Indirect and PreDecrement using index Y.
1793 *
1794 * Opcode : 1001 000d dddd 1010
1795 * Usage : LD Rd, -Y
1796 * Operation : Y <- Y - 1, Rd <- (Y)
1797 * Flags : None
1798 * Num Clocks : 2
1799 */
1800 uint16_t Y;
1801
1802 int Rd = arg1;
1803
1804 if ((Rd == 28) || (Rd == 29))
1805 avr_error ("Results of operation are undefined");
1806
1807 /* Y is R29:R28 */
1808 Y = (avr_core_gpwr_get (core, 29) << 8) + avr_core_gpwr_get (core, 28);
1809
1810 /* Perform pre-decrement */
1811 Y -= 1;
1812 avr_core_gpwr_set (core, 28, Y & 0xff);
1813 avr_core_gpwr_set (core, 29, Y >> 8);
1814
1815 avr_core_gpwr_set (core, Rd, avr_core_mem_read (core, Y));
1816
1817 avr_core_PC_incr (core, 1);
1818 avr_core_inst_CKS_set (core, 2);
1819
1820 return opcode_LD_Y_decr;
1821 }
1822
1823 static int
1824 avr_op_LD_Y_incr (AvrCore *core, uint16_t opcode, unsigned int arg1,
1825 unsigned int arg2)
1826 {
1827 /*
1828 * Load Indirect and Post-Increment using index Y.
1829 *
1830 * Opcode : 1001 000d dddd 1001
1831 * Usage : LD Rd, Y+
1832 * Operation : Rd <- (Y), Y <- Y + 1
1833 * Flags : None
1834 * Num Clocks : 2
1835 */
1836 uint16_t Y;
1837
1838 int Rd = arg1;
1839
1840 if ((Rd == 28) || (Rd == 29))
1841 avr_error ("Results of operation are undefined");
1842
1843 /* Y is R29:R28 */
1844 Y = (avr_core_gpwr_get (core, 29) << 8) + avr_core_gpwr_get (core, 28);
1845
1846 avr_core_gpwr_set (core, Rd, avr_core_mem_read (core, Y));
1847
1848 /* Perform post-increment */
1849 Y += 1;
1850 avr_core_gpwr_set (core, 28, Y & 0xff);
1851 avr_core_gpwr_set (core, 29, Y >> 8);
1852
1853 avr_core_PC_incr (core, 1);
1854 avr_core_inst_CKS_set (core, 2);
1855
1856 return opcode_LD_Y_incr;
1857 }
1858
1859 static int
1860 avr_op_LD_Z_incr (AvrCore *core, uint16_t opcode, unsigned int arg1,
1861 unsigned int arg2)
1862 {
1863 /*
1864 * Load Indirect and Post-Increment using index Z.
1865 *
1866 * Opcode : 1001 000d dddd 0001
1867 * Usage : LD Rd, Z+
1868 * Operation : Rd <- (Z), Z <- Z+1
1869 * Flags : None
1870 * Num Clocks : 2
1871 */
1872 uint16_t Z;
1873
1874 int Rd = arg1;
1875
1876 if ((Rd == 30) || (Rd == 31))
1877 avr_error ("Results of operation are undefined");
1878
1879 /* Z is R31:R30 */
1880 Z = (avr_core_gpwr_get (core, 31) << 8) + avr_core_gpwr_get (core, 30);
1881
1882 avr_core_gpwr_set (core, Rd, avr_core_mem_read (core, Z));
1883
1884 /* Perform post-increment */
1885 Z += 1;
1886 avr_core_gpwr_set (core, 30, Z & 0xff);
1887 avr_core_gpwr_set (core, 31, Z >> 8);
1888
1889 avr_core_PC_incr (core, 1);
1890 avr_core_inst_CKS_set (core, 2);
1891
1892 return opcode_LD_Z_incr;
1893 }
1894
1895 static int
1896 avr_op_LD_Z_decr (AvrCore *core, uint16_t opcode, unsigned int arg1,
1897 unsigned int arg2)
1898 {
1899 /*
1900 * Load Indirect and Pre-Decrement using index Z.
1901 *
1902 * Opcode : 1001 000d dddd 0010
1903 * Usage : LD Rd, -Z
1904 * Operation : Z <- Z - 1, Rd <- (Z)
1905 * Flags : None
1906 * Num Clocks : 2
1907 */
1908 uint16_t Z;
1909
1910 int Rd = arg1;
1911
1912 if ((Rd == 30) || (Rd == 31))
1913 avr_error ("Results of operation are undefined");
1914
1915 /* Z is R31:R30 */
1916 Z = (avr_core_gpwr_get (core, 31) << 8) + avr_core_gpwr_get (core, 30);
1917
1918 /* Perform pre-decrement */
1919 Z -= 1;
1920 avr_core_gpwr_set (core, 30, Z & 0xff);
1921 avr_core_gpwr_set (core, 31, Z >> 8);
1922
1923 avr_core_gpwr_set (core, Rd, avr_core_mem_read (core, Z));
1924
1925 avr_core_PC_incr (core, 1);
1926 avr_core_inst_CKS_set (core, 2);
1927
1928 return opcode_LD_Z_decr;
1929 }
1930
1931 static int
1932 avr_op_LPM_Z (AvrCore *core, uint16_t opcode, unsigned int arg1,
1933 unsigned int arg2)
1934 {
1935 /*
1936 * Load Program Memory.
1937 *
1938 * Opcode : 1001 000d dddd 0100
1939 * Usage : LPM Rd, Z
1940 * Operation : Rd <- (Z)
1941 * Flags : None
1942 * Num Clocks : 3
1943 */
1944 uint16_t Z, high_byte;
1945 uint16_t data;
1946
1947 int Rd = arg1;
1948
1949 /* Z is R31:R30 */
1950 Z = (avr_core_gpwr_get (core, 31) << 8) + avr_core_gpwr_get (core, 30);
1951 high_byte = Z & 0x1;
1952
1953 /* FIXME: I don't know if this is the right thing to do. I'm not sure that
1954 I understand what the instruction data sheet is saying about Z.
1955 Dividing by 2 seems to give the address that we want though. */
1956
1957 data = flash_read (core->flash, Z / 2);
1958
1959 if (high_byte == 1)
1960 avr_core_gpwr_set (core, Rd, data >> 8);
1961 else
1962 avr_core_gpwr_set (core, Rd, data & 0xff);
1963
1964 avr_core_PC_incr (core, 1);
1965 avr_core_inst_CKS_set (core, 3);
1966
1967 return opcode_LPM_Z;
1968 }
1969
1970 static int
1971 avr_op_LPM (AvrCore *core, uint16_t opcode, unsigned int arg1,
1972 unsigned int arg2)
1973 {
1974 /* Load Program Memory.
1975 *
1976 * This the same as avr_op_LPM_Z with Rd = R0.
1977 *
1978 * Opcode : 1001 0101 1100 1000
1979 * Usage : LPM
1980 * Operation : R0 <- (Z)
1981 * Flags : None
1982 * Num Clocks : 3
1983 */
1984 return avr_op_LPM_Z (core, 0x9004, 0, arg2);
1985 }
1986
1987 static int
1988 avr_op_LPM_Z_incr (AvrCore *core, uint16_t opcode, unsigned int arg1,
1989 unsigned int arg2)
1990 {
1991 /*
1992 * Load Program Memory and Post-Incr.
1993 *
1994 * Opcode : 1001 000d dddd 0101
1995 * Usage : LPM Rd, Z+
1996 * Operation : Rd <- (Z), Z <- Z + 1
1997 * Flags : None
1998 * Num Clocks : 3
1999 */
2000 uint16_t Z, high_byte;
2001 uint16_t data;
2002
2003 int Rd = arg1;
2004
2005 if ((Rd == 30) || (Rd == 31))
2006 avr_error ("Results of operation are undefined");
2007
2008 /* Z is R31:R30 */
2009 Z = (avr_core_gpwr_get (core, 31) << 8) + avr_core_gpwr_get (core, 30);
2010 high_byte = Z & 0x1;
2011
2012 /* FIXME: I don't know if this is the right thing to do. I'm not sure that
2013 I understand what the instruction data sheet is saying about Z.
2014 Dividing by 2 seems to give the address that we want though. */
2015
2016 data = flash_read (core->flash, Z / 2);
2017
2018 if (high_byte == 1)
2019 avr_core_gpwr_set (core, Rd, data >> 8);
2020 else
2021 avr_core_gpwr_set (core, Rd, data & 0xff);
2022
2023 /* Perform post-increment */
2024 Z += 1;
2025 avr_core_gpwr_set (core, 30, Z & 0xff);
2026 avr_core_gpwr_set (core, 31, Z >> 8);
2027
2028 avr_core_PC_incr (core, 1);
2029 avr_core_inst_CKS_set (core, 3);
2030
2031 return opcode_LPM_Z_incr;
2032 }
2033
2034 static int
2035 avr_op_LSR (AvrCore *core, uint16_t opcode, unsigned int arg1,
2036 unsigned int arg2)
2037 {
2038 /*
2039 * Logical Shift Right.
2040 *
2041 * Opcode : 1001 010d dddd 0110
2042 * Usage : LSR Rd
2043 * Operation : Rd(n) <- Rd(n+1), Rd(7) <- 0, C <- Rd(0)
2044 * Flags : Z,C,N,V,S
2045 * Num Clocks : 1
2046 */
2047 int Z, C, N, V, S;
2048
2049 int Rd = arg1;
2050 uint8_t rd = avr_core_gpwr_get (core, Rd);
2051
2052 uint8_t res = (rd >> 1) & 0x7f;
2053
2054 uint8_t sreg = avr_core_sreg_get (core);
2055
2056 sreg = set_bit_in_byte (sreg, SREG_C, C = (rd & 0x1));
2057 sreg = set_bit_in_byte (sreg, SREG_N, N = (0));
2058 sreg = set_bit_in_byte (sreg, SREG_V, V = (N ^ C));
2059 sreg = set_bit_in_byte (sreg, SREG_S, S = (N ^ V));
2060 sreg = set_bit_in_byte (sreg, SREG_Z, Z = ((res & 0xff) == 0));
2061
2062 avr_core_sreg_set (core, sreg);
2063
2064 avr_core_gpwr_set (core, Rd, res);
2065
2066 avr_core_PC_incr (core, 1);
2067 avr_core_inst_CKS_set (core, 1);
2068
2069 return opcode_LSR;
2070 }
2071
2072 static int
2073 avr_op_MOV (AvrCore *core, uint16_t opcode, unsigned int arg1,
2074 unsigned int arg2)
2075 {
2076 /* Copy Register.
2077 *
2078 * Opcode : 0010 11rd dddd rrrr
2079 * Usage : MOV Rd, Rr
2080 * Operation : Rd <- Rr
2081 * Flags : None
2082 * Num Clocks : 1
2083 */
2084 int Rd = arg1;
2085 int Rr = arg2;
2086
2087 avr_core_gpwr_set (core, Rd, avr_core_gpwr_get (core, Rr));
2088
2089 avr_core_PC_incr (core, 1);
2090 avr_core_inst_CKS_set (core, 1);
2091
2092 return opcode_MOV;
2093 }
2094
2095 static int
2096 avr_op_MOVW (AvrCore *core, uint16_t opcode, unsigned int arg1,
2097 unsigned int arg2)
2098 {
2099 /*
2100 *Copy Register Pair.
2101 *
2102 * Opcode : 0000 0001 dddd rrrr
2103 * Usage : MOVW Rd, Rr
2104 * Operation : Rd+1:Rd <- Rr+1:Rr
2105 * Flags : None
2106 * Num Clocks : 1
2107 */
2108 int Rd = arg1;
2109 int Rr = arg2;
2110
2111 /* get_rd_4() returns 16 <= r <= 31, but here Rd and Rr */
2112 /* are even from 0 <= r <= 30. So we translate. */
2113 Rd = (Rd - 16) * 2;
2114 Rr = (Rr - 16) * 2;
2115
2116 avr_core_gpwr_set (core, Rd, avr_core_gpwr_get (core, Rr));
2117 avr_core_gpwr_set (core, Rd + 1, avr_core_gpwr_get (core, Rr + 1));
2118
2119 avr_core_PC_incr (core, 1);
2120 avr_core_inst_CKS_set (core, 1);
2121
2122 return opcode_MOVW;
2123 }
2124
2125 static int
2126 avr_op_MUL (AvrCore *core, uint16_t opcode, unsigned int arg1,
2127 unsigned int arg2)
2128 {
2129 /*
2130 * Mult Unsigned.
2131 *
2132 * Opcode : 1001 11rd dddd rrrr
2133 * Usage : MUL Rd, Rr
2134 * Operation : R1:R0 <- Rd * Rr (UU)
2135 * Flags : Z,C
2136 * Num Clocks : 2
2137 */
2138 int Rd = arg1;
2139 int Rr = arg2;
2140
2141 uint8_t rd = avr_core_gpwr_get (core, Rd);
2142 uint8_t rr = avr_core_gpwr_get (core, Rr);
2143
2144 uint16_t res = rd * rr;
2145
2146 uint8_t sreg = avr_core_sreg_get (core);
2147
2148 sreg = set_bit_in_byte (sreg, SREG_Z, ((res & 0xffff) == 0));
2149 sreg = set_bit_in_byte (sreg, SREG_C, ((res >> 15) & 0x1));
2150
2151 avr_core_sreg_set (core, sreg);
2152
2153 /* result goes in R1:R0 */
2154
2155 avr_core_gpwr_set (core, 1, res >> 8);
2156 avr_core_gpwr_set (core, 0, res & 0xff);
2157
2158 avr_core_PC_incr (core, 1);
2159 avr_core_inst_CKS_set (core, 2);
2160
2161 return opcode_MUL;
2162 }
2163
2164 static int
2165 avr_op_MULS (AvrCore *core, uint16_t opcode, unsigned int arg1,
2166 unsigned int arg2)
2167 {
2168 /*
2169 * Mult Signed.
2170 *
2171 * Opcode : 0000 0010 dddd rrrr
2172 * Usage : MULS Rd, Rr
2173 * Operation : R1:R0 <- Rd * Rr (SS)
2174 * Flags : Z,C
2175 * Num Clocks : 2
2176 */
2177 int Rd = arg1;
2178 int Rr = arg2;
2179
2180 int8_t rd = (int8_t) avr_core_gpwr_get (core, Rd);
2181 int8_t rr = (int8_t) avr_core_gpwr_get (core, Rr);
2182 int16_t res = rd * rr;
2183
2184 uint8_t sreg = avr_core_sreg_get (core);
2185
2186 sreg = set_bit_in_byte (sreg, SREG_Z, ((res & 0xffff) == 0));
2187 sreg = set_bit_in_byte (sreg, SREG_C, ((res >> 15) & 0x1));
2188
2189 avr_core_sreg_set (core, sreg);
2190
2191 /* result goes in R1:R0 */
2192 avr_core_gpwr_set (core, 1, res >> 8);
2193 avr_core_gpwr_set (core, 0, res & 0xff);
2194
2195 avr_core_PC_incr (core, 1);
2196 avr_core_inst_CKS_set (core, 2);
2197
2198 return opcode_MULS;
2199 }
2200
2201 static int
2202 avr_op_MULSU (AvrCore *core, uint16_t opcode, unsigned int arg1,
2203 unsigned int arg2)
2204 {
2205 /*
2206 * Mult Signed with Unsigned.
2207 *
2208 * Rd(unsigned),Rr(signed), result (signed)
2209 *
2210 * Opcode : 0000 0011 0ddd 0rrr
2211 * Usage : MULSU Rd, Rr
2212 * Operation : R1:R0 <- Rd * Rr (SU)
2213 * Flags : Z,C
2214 * Num Clocks : 2
2215 */
2216 int Rd = arg1;
2217 int Rr = arg2;
2218
2219 int8_t rd = (int8_t) avr_core_gpwr_get (core, Rd);
2220 uint8_t rr = avr_core_gpwr_get (core, Rr);
2221
2222 int16_t res = rd * rr;
2223
2224 uint8_t sreg = avr_core_sreg_get (core);
2225
2226 sreg = set_bit_in_byte (sreg, SREG_Z, ((res & 0xffff) == 0));
2227 sreg = set_bit_in_byte (sreg, SREG_C, ((res >> 15) & 0x1));
2228
2229 avr_core_sreg_set (core, sreg);
2230
2231 /* result goes in R1:R0 */
2232 avr_core_gpwr_set (core, 1, res >> 8);
2233 avr_core_gpwr_set (core, 0, res & 0xff);
2234
2235 avr_core_PC_incr (core, 1);
2236 avr_core_inst_CKS_set (core, 2);
2237
2238 return opcode_MULSU;
2239 }
2240
2241 static int
2242 avr_op_NEG (AvrCore *core, uint16_t opcode, unsigned int arg1,
2243 unsigned int arg2)
2244 {
2245 /*
2246 * Two's Complement.
2247 *
2248 * Opcode : 1001 010d dddd 0001
2249 * Usage : NEG Rd
2250 * Operation : Rd <- $00 - Rd
2251 * Flags : Z,C,N,V,S,H
2252 * Num Clocks : 1
2253 */
2254 int Z, C, N, V, S, H;
2255
2256 int Rd = arg1;
2257
2258 uint8_t rd = avr_core_gpwr_get (core, Rd);
2259 uint8_t res = (0x0 - rd) & 0xff;
2260
2261 uint8_t sreg = avr_core_sreg_get (core);
2262
2263 sreg = set_bit_in_byte (sreg, SREG_H, H =
2264 (((res >> 3) | (rd >> 3)) & 0x1));
2265 sreg = set_bit_in_byte (sreg, SREG_V, V = (res == 0x80));
2266 sreg = set_bit_in_byte (sreg, SREG_N, N = ((res >> 7) & 0x1));
2267 sreg = set_bit_in_byte (sreg, SREG_S, S = (N ^ V));
2268 sreg = set_bit_in_byte (sreg, SREG_Z, Z = (res == 0x0));
2269 sreg = set_bit_in_byte (sreg, SREG_C, C = (res != 0x0));
2270
2271 avr_core_sreg_set (core, sreg);
2272
2273 avr_core_gpwr_set (core, Rd, res);
2274
2275 avr_core_PC_incr (core, 1);
2276 avr_core_inst_CKS_set (core, 1);
2277
2278 return opcode_NEG;
2279 }
2280
2281 static int
2282 avr_op_NOP (AvrCore *core, uint16_t opcode, unsigned int arg1,
2283 unsigned int arg2)
2284 {
2285 /*
2286 * No Operation.
2287 *
2288 * Opcode : 0000 0000 0000 0000
2289 * Usage : NOP
2290 * Operation : None
2291 * Flags : None
2292 * Num Clocks : 1
2293 */
2294 avr_core_PC_incr (core, 1);
2295 avr_core_inst_CKS_set (core, 1);
2296 return opcode_NOP;
2297 }
2298
2299 static int
2300 avr_op_OR (AvrCore *core, uint16_t opcode, unsigned int arg1,
2301 unsigned int arg2)
2302 {
2303 /*
2304 * Logical OR.
2305 *
2306 * Opcode : 0010 10rd dddd rrrr
2307 * Usage : OR Rd, Rr
2308 * Operation : Rd <- Rd or Rr
2309 * Flags : Z,N,V,S
2310 * Num Clocks : 1
2311 */
2312 int Z, N, V, S;
2313
2314 int Rd = arg1;
2315 int Rr = arg2;
2316
2317 uint8_t res = avr_core_gpwr_get (core, Rd) | avr_core_gpwr_get (core, Rr);
2318
2319 uint8_t sreg = avr_core_sreg_get (core);
2320
2321 sreg = set_bit_in_byte (sreg, SREG_V, V = (0));
2322 sreg = set_bit_in_byte (sreg, SREG_N, N = ((res >> 7) & 0x1));
2323 sreg = set_bit_in_byte (sreg, SREG_S, S = (N ^ V));
2324 sreg = set_bit_in_byte (sreg, SREG_Z, Z = (res == 0x0));
2325
2326 avr_core_sreg_set (core, sreg);
2327
2328 avr_core_gpwr_set (core, Rd, res);
2329
2330 avr_core_PC_incr (core, 1);
2331 avr_core_inst_CKS_set (core, 1);
2332
2333 return opcode_OR;
2334 }
2335
2336 static int
2337 avr_op_ORI (AvrCore *core, uint16_t opcode, unsigned int arg1,
2338 unsigned int arg2)
2339 {
2340 /*
2341 * Logical OR with Immed.
2342 *
2343 * Opcode : 0110 KKKK dddd KKKK
2344 * Usage : ORI Rd, K
2345 * Operation : Rd <- Rd or K
2346 * Flags : Z,N,V,S
2347 * Num Clocks : 1
2348 */
2349 int Z, N, V, S;
2350
2351 int Rd = arg1;
2352 uint8_t K = arg2;
2353
2354 uint8_t res = avr_core_gpwr_get (core, Rd) | K;
2355
2356 uint8_t sreg = avr_core_sreg_get (core);
2357
2358 sreg = set_bit_in_byte (sreg, SREG_V, V = (0));
2359 sreg = set_bit_in_byte (sreg, SREG_N, N = ((res >> 7) & 0x1));
2360 sreg = set_bit_in_byte (sreg, SREG_S, S = (N ^ V));
2361 sreg = set_bit_in_byte (sreg, SREG_Z, Z = (res == 0x0));
2362
2363 avr_core_sreg_set (core, sreg);
2364
2365 avr_core_gpwr_set (core, Rd, res);
2366
2367 avr_core_PC_incr (core, 1);
2368 avr_core_inst_CKS_set (core, 1);
2369
2370 return opcode_ORI;
2371 }
2372
2373 static int
2374 avr_op_OUT (AvrCore *core, uint16_t opcode, unsigned int arg1,
2375 unsigned int arg2)
2376 {
2377 /*
2378 * Out To I/O Location.
2379 *
2380 * Opcode : 1011 1AAd dddd AAAA
2381 * Usage : OUT A, Rd
2382 * Operation : I/O(A) <- Rd
2383 * Flags : None
2384 * Num Clocks : 1
2385 */
2386
2387 /* Even though the args in the comment are reversed (out arg2, arg1), the
2388 following is correct: Rd=arg1, A=arg2. */
2389 int Rd = arg1;
2390 int A = arg2;
2391
2392 avr_core_io_write (core, A, avr_core_gpwr_get (core, Rd));
2393
2394 avr_core_PC_incr (core, 1);
2395 avr_core_inst_CKS_set (core, 1);
2396
2397 return opcode_OUT;
2398 }
2399
2400 static int
2401 avr_op_POP (AvrCore *core, uint16_t opcode, unsigned int arg1,
2402 unsigned int arg2)
2403 {
2404 /*
2405 * Pop Register from Stack.
2406 *
2407 * Opcode : 1001 000d dddd 1111
2408 * Usage : POP Rd
2409 * Operation : Rd <- STACK
2410 * Flags : None
2411 * Num Clocks : 2
2412 */
2413 int Rd = arg1;
2414
2415 avr_core_gpwr_set (core, Rd, avr_core_stack_pop (core, 1));
2416
2417 avr_core_PC_incr (core, 1);
2418 avr_core_inst_CKS_set (core, 2);
2419
2420 return opcode_POP;
2421 }
2422
2423 static int
2424 avr_op_PUSH (AvrCore *core, uint16_t opcode, unsigned int arg1,
2425 unsigned int arg2)
2426 {
2427 /*
2428 * Push Register on Stack.
2429 *
2430 * Opcode : 1001 001d dddd 1111
2431 * Usage : PUSH Rd
2432 * Operation : STACK <- Rd
2433 * Flags : None
2434 * Num Clocks : 2
2435 */
2436 int Rd = arg1;
2437
2438 avr_core_stack_push (core, 1, avr_core_gpwr_get (core, Rd));
2439
2440 avr_core_PC_incr (core, 1);
2441 avr_core_inst_CKS_set (core, 2);
2442
2443 return opcode_PUSH;
2444 }
2445
2446 static int
2447 avr_op_RCALL (AvrCore *core, uint16_t opcode, unsigned int arg1,
2448 unsigned int arg2)
2449 {
2450 /*
2451 * Relative Call Subroutine.
2452 *
2453 * Opcode : 1101 kkkk kkkk kkkk
2454 * Usage : RCALL k
2455 * Operation : PC <- PC + k + 1
2456 * Flags : None
2457 * Num Clocks : 3 / 4
2458 */
2459 int k = arg1;
2460
2461 int pc = avr_core_PC_get (core);
2462 int pc_bytes = avr_core_PC_size (core);
2463
2464 avr_core_stack_push (core, pc_bytes, pc + 1);
2465
2466 avr_core_PC_incr (core, k + 1);
2467 avr_core_inst_CKS_set (core, pc_bytes + 1);
2468
2469 return opcode_RCALL;
2470 }
2471
2472 static int
2473 avr_op_RET (AvrCore *core, uint16_t opcode, unsigned int arg1,
2474 unsigned int arg2)
2475 {
2476 /*
2477 * Subroutine Return.
2478 *
2479 * Opcode : 1001 0101 0000 1000
2480 * Usage : RET
2481 * Operation : PC <- STACK
2482 * Flags : None
2483 * Num Clocks : 4 / 5
2484 */
2485 int pc_bytes = avr_core_PC_size (core);
2486 int pc = avr_core_stack_pop (core, pc_bytes);
2487
2488 avr_core_PC_set (core, pc);
2489 avr_core_inst_CKS_set (core, pc_bytes + 2);
2490
2491 return opcode_RET;
2492 }
2493
2494 static int
2495 avr_op_RETI (AvrCore *core, uint16_t opcode, unsigned int arg1,
2496 unsigned int arg2)
2497 {
2498 /*
2499 * Interrupt Return.
2500 *
2501 * Opcode : 1001 0101 0001 1000
2502 * Usage : RETI
2503 * Operation : PC <- STACK
2504 * Flags : I
2505 * Num Clocks : 4 / 5
2506 */
2507 int pc_bytes = avr_core_PC_size (core);
2508 int pc = avr_core_stack_pop (core, pc_bytes);
2509
2510 avr_core_PC_set (core, pc);
2511 avr_core_inst_CKS_set (core, pc_bytes + 2);
2512
2513 avr_core_sreg_set_bit (core, SREG_I, 1);
2514
2515 return opcode_RETI;
2516 }
2517
2518 static int
2519 avr_op_RJMP (AvrCore *core, uint16_t opcode, unsigned int arg1,
2520 unsigned int arg2)
2521 {
2522 /*
2523 * Relative Jump.
2524 *
2525 * Opcode : 1100 kkkk kkkk kkkk
2526 * Usage : RJMP k
2527 * Operation : PC <- PC + k + 1
2528 * Flags : None
2529 * Num Clocks : 2
2530 */
2531 int k = arg1;
2532
2533 avr_core_PC_incr (core, k + 1);
2534 avr_core_inst_CKS_set (core, 2);
2535
2536 return opcode_RJMP;
2537 }
2538
2539 static int
2540 avr_op_ROR (AvrCore *core, uint16_t opcode, unsigned int arg1,
2541 unsigned int arg2)
2542 {
2543 /*
2544 * Rotate Right Though Carry.
2545 *
2546 * Opcode : 1001 010d dddd 0111
2547 * Usage : ROR Rd
2548 * Operation : Rd(7) <- C, Rd(n) <- Rd(n+1), C <- Rd(0)
2549 * Flags : Z,C,N,V,S
2550 * Num Clocks : 1
2551 */
2552 int Z, C, N, V, S;
2553
2554 int Rd = arg1;
2555 uint8_t rd = avr_core_gpwr_get (core, Rd);
2556
2557 uint8_t res =
2558 (rd >> 1) | ((avr_core_sreg_get_bit (core, SREG_C) << 7) & 0x80);
2559
2560 uint8_t sreg = avr_core_sreg_get (core);
2561
2562 sreg = set_bit_in_byte (sreg, SREG_C, C = (rd & 0x1));
2563 sreg = set_bit_in_byte (sreg, SREG_N, N = ((res >> 7) & 0x1));
2564 sreg = set_bit_in_byte (sreg, SREG_V, V = (N ^ C));
2565 sreg = set_bit_in_byte (sreg, SREG_S, S = (N ^ V));
2566 sreg = set_bit_in_byte (sreg, SREG_Z, Z = (res == 0));
2567
2568 avr_core_sreg_set (core, sreg);
2569
2570 avr_core_gpwr_set (core, Rd, res);
2571
2572 avr_core_PC_incr (core, 1);
2573 avr_core_inst_CKS_set (core, 1);
2574
2575 return opcode_ROR;
2576 }
2577
2578 static int
2579 avr_op_SBC (AvrCore *core, uint16_t opcode, unsigned int arg1,
2580 unsigned int arg2)
2581 {
2582 /*
2583 * Subtract with Carry.
2584 *
2585 * Opcode : 0000 10rd dddd rrrr
2586 * Usage : SBC Rd, Rr
2587 * Operation : Rd <- Rd - Rr - C
2588 * Flags : Z,C,N,V,S,H
2589 * Num Clocks : 1
2590 */
2591 int Z, C, N, V, S, H;
2592
2593 int Rd = arg1;
2594 int Rr = arg2;
2595
2596 uint8_t rd = avr_core_gpwr_get (core, Rd);
2597 uint8_t rr = avr_core_gpwr_get (core, Rr);
2598
2599 uint8_t res = rd - rr - avr_core_sreg_get_bit (core, SREG_C);
2600
2601 uint8_t sreg = avr_core_sreg_get (core);
2602
2603 sreg = set_bit_in_byte (sreg, SREG_H, H =
2604 (get_sub_carry (res, rd, rr, 3)));
2605 sreg = set_bit_in_byte (sreg, SREG_V, V =
2606 (get_sub_overflow (res, rd, rr)));
2607 sreg = set_bit_in_byte (sreg, SREG_N, N = ((res >> 7) & 0x1));
2608 sreg = set_bit_in_byte (sreg, SREG_S, S = (N ^ V));
2609 sreg = set_bit_in_byte (sreg, SREG_C, C =
2610 (get_sub_carry (res, rd, rr, 7)));
2611
2612 if ((res & 0xff) != 0)
2613 sreg = set_bit_in_byte (sreg, SREG_Z, Z = (0));
2614
2615 avr_core_sreg_set (core, sreg);
2616
2617 avr_core_gpwr_set (core, Rd, res);
2618
2619 avr_core_PC_incr (core, 1);
2620 avr_core_inst_CKS_set (core, 1);
2621
2622 return opcode_SBC;
2623 }
2624
2625 static int
2626 avr_op_SBCI (AvrCore *core, uint16_t opcode, unsigned int arg1,
2627 unsigned int arg2)
2628 {
2629 /*
2630 * Subtract Immediate with Carry.
2631 *
2632 * Opcode : 0100 KKKK dddd KKKK
2633 * Usage : SBCI Rd, K
2634 * Operation : Rd <- Rd - K - C
2635 * Flags : Z,C,N,V,S,H
2636 * Num Clocks : 1
2637 */
2638 int Z, C, N, V, S, H;
2639
2640 int Rd = arg1;
2641 uint8_t K = arg2;
2642
2643 uint8_t rd = avr_core_gpwr_get (core, Rd);
2644
2645 uint8_t res = rd - K - avr_core_sreg_get_bit (core, SREG_C);
2646
2647 uint8_t sreg = avr_core_sreg_get (core);
2648
2649 sreg = set_bit_in_byte (sreg, SREG_H, H =
2650 (get_sub_carry (res, rd, K, 3)));
2651 sreg = set_bit_in_byte (sreg, SREG_V, V =
2652 (get_sub_overflow (res, rd, K)));
2653 sreg = set_bit_in_byte (sreg, SREG_N, N = ((res >> 7) & 0x1));
2654 sreg = set_bit_in_byte (sreg, SREG_S, S = (N ^ V));
2655 sreg = set_bit_in_byte (sreg, SREG_C, C =
2656 (get_sub_carry (res, rd, K, 7)));
2657
2658 if ((res & 0xff) != 0)
2659 sreg = set_bit_in_byte (sreg, SREG_Z, Z = 0);
2660
2661 avr_core_sreg_set (core, sreg);
2662
2663 avr_core_gpwr_set (core, Rd, res);
2664
2665 avr_core_PC_incr (core, 1);
2666 avr_core_inst_CKS_set (core, 1);
2667
2668 return opcode_SBCI;
2669 }
2670
2671 static int
2672 avr_op_SBI (AvrCore *core, uint16_t opcode, unsigned int arg1,
2673 unsigned int arg2)
2674 {
2675 /*
2676 * Set Bit in I/O Register.
2677 *
2678 * Opcode : 1001 1010 AAAA Abbb
2679 * Usage : SBI A, b
2680 * Operation : I/O(A, b) <- 1
2681 * Flags : None
2682 * Num Clocks : 2
2683 */
2684 int A = arg1;
2685 int b = arg2;
2686
2687 uint8_t val = avr_core_io_read (core, A);
2688 avr_core_io_write (core, A, val | (1 << b));
2689
2690 avr_core_PC_incr (core, 1);
2691 avr_core_inst_CKS_set (core, 2);
2692
2693 return opcode_SBI;
2694 }
2695
2696 static int
2697 avr_op_SBIC (AvrCore *core, uint16_t opcode, unsigned int arg1,
2698 unsigned int arg2)
2699 {
2700 /*
2701 * Skip if Bit in I/O Reg Cleared.
2702 *
2703 * Opcode : 1001 1001 AAAA Abbb
2704 * Usage : SBIC A, b
2705 * Operation : if (I/O(A,b) = 0) PC <- PC + 2 or 3
2706 * Flags : None
2707 * Num Clocks : 1 / 2 / 3
2708 */
2709 int skip;
2710
2711 int A = arg1;
2712 int b = arg2;
2713
2714 if (is_next_inst_2_words (core))
2715 skip = 3;
2716 else
2717 skip = 2;
2718
2719 if ((avr_core_io_read (core, A) & (1 << b)) == 0)
2720 {
2721 avr_core_PC_incr (core, skip);
2722 avr_core_inst_CKS_set (core, skip);
2723 }
2724 else
2725 {
2726 avr_core_PC_incr (core, 1);
2727 avr_core_inst_CKS_set (core, 1);
2728 }
2729
2730 return opcode_SBIC;
2731 }
2732
2733 static int
2734 avr_op_SBIS (AvrCore *core, uint16_t opcode, unsigned int arg1,
2735 unsigned int arg2)
2736 {
2737 /*
2738 * Skip if Bit in I/O Reg Set.
2739 *
2740 * Opcode : 1001 1011 AAAA Abbb
2741 * Usage : SBIS A, b
2742 * Operation : if (I/O(A,b) = 1) PC <- PC + 2 or 3
2743 * Flags : None
2744 * Num Clocks : 1 / 2 / 3
2745 */
2746 int skip;
2747
2748 int A = arg1;
2749 int b = arg2;
2750
2751 if (is_next_inst_2_words (core))
2752 skip = 3;
2753 else
2754 skip = 2;
2755
2756 if ((avr_core_io_read (core, A) & (1 << b)) != 0)
2757 {
2758 avr_core_PC_incr (core, skip);
2759 avr_core_inst_CKS_set (core, skip);
2760 }
2761 else
2762 {
2763 avr_core_PC_incr (core, 1);
2764 avr_core_inst_CKS_set (core, 1);
2765 }
2766
2767 return opcode_SBIS;
2768 }
2769
2770 static int
2771 avr_op_SBIW (AvrCore *core, uint16_t opcode, unsigned int arg1,
2772 unsigned int arg2)
2773 {
2774 /*
2775 * Subtract Immed from Word.
2776 *
2777 * Opcode : 1001 0111 KKdd KKKK
2778 * Usage : SBIW Rd, K
2779 * Operation : Rd+1:Rd <- Rd+1:Rd - K
2780 * Flags : Z,C,N,V,S
2781 * Num Clocks : 2
2782 */
2783 int Z, C, N, V, S;
2784
2785 int Rd = arg1;
2786 uint8_t K = arg2;
2787
2788 uint8_t rdl = avr_core_gpwr_get (core, Rd);
2789 uint8_t rdh = avr_core_gpwr_get (core, Rd + 1);
2790
2791 uint16_t rd = (rdh << 8) + rdl;
2792
2793 uint16_t res = rd - K;
2794
2795 uint8_t sreg = avr_core_sreg_get (core);
2796
2797 sreg = set_bit_in_byte (sreg, SREG_V, V =
2798 ((rdh >> 7 & 0x1) & ~(res >> 15 & 0x1)));
2799 sreg = set_bit_in_byte (sreg, SREG_N, N = ((res >> 15) & 0x1));
2800 sreg = set_bit_in_byte (sreg, SREG_S, S = (N ^ V));
2801 sreg = set_bit_in_byte (sreg, SREG_Z, Z = ((res & 0xffff) == 0));
2802 sreg = set_bit_in_byte (sreg, SREG_C, C =
2803 ((res >> 15 & 0x1) & ~(rdh >> 7 & 0x1)));
2804
2805 avr_core_sreg_set (core, sreg);
2806
2807 avr_core_gpwr_set (core, Rd, res & 0xff);
2808 avr_core_gpwr_set (core, Rd + 1, res >> 8);
2809
2810 avr_core_PC_incr (core, 1);
2811 avr_core_inst_CKS_set (core, 2);
2812
2813 return opcode_SBIW;
2814 }
2815
2816 static int
2817 avr_op_SBRC (AvrCore *core, uint16_t opcode, unsigned int arg1,
2818 unsigned int arg2)
2819 {
2820 /*
2821 * Skip if Bit in Reg Cleared.
2822 *
2823 * Opcode : 1111 110d dddd 0bbb
2824 * Usage : SBRC Rd, b
2825 * Operation : if (Rd(b) = 0) PC <- PC + 2 or 3
2826 * Flags : None
2827 * Num Clocks : 1 / 2 / 3
2828 */
2829 int skip;
2830
2831 int Rd = arg1;
2832 int b = arg2;
2833
2834 if (is_next_inst_2_words (core))
2835 skip = 3;
2836 else
2837 skip = 2;
2838
2839 if (((avr_core_gpwr_get (core, Rd) >> b) & 0x1) == 0)
2840 {
2841 avr_core_PC_incr (core, skip);
2842 avr_core_inst_CKS_set (core, skip);
2843 }
2844 else
2845 {
2846 avr_core_PC_incr (core, 1);
2847 avr_core_inst_CKS_set (core, 1);
2848 }
2849
2850 return opcode_SBRC;
2851 }
2852
2853 static int
2854 avr_op_SBRS (AvrCore *core, uint16_t opcode, unsigned int arg1,
2855 unsigned int arg2)
2856 {
2857 /*
2858 * Skip if Bit in Reg Set.
2859 *
2860 * Opcode : 1111 111d dddd 0bbb
2861 * Usage : SBRS Rd, b
2862 * Operation : if (Rd(b) = 1) PC <- PC + 2 or 3
2863 * Flags : None
2864 * Num Clocks : 1 / 2 / 3
2865 */
2866 int skip;
2867
2868 int Rd = arg1;
2869 int b = arg2;
2870
2871 if (is_next_inst_2_words (core))
2872 skip = 3;
2873 else
2874 skip = 2;
2875
2876 if (((avr_core_gpwr_get (core, Rd) >> b) & 0x1) != 0)
2877 {
2878 avr_core_PC_incr (core, skip);
2879 avr_core_inst_CKS_set (core, skip);
2880 }
2881 else
2882 {
2883 avr_core_PC_incr (core, 1);
2884 avr_core_inst_CKS_set (core, 1);
2885 }
2886
2887 return opcode_SBRS;
2888 }
2889
2890 static int
2891 avr_op_SLEEP (AvrCore *core, uint16_t opcode, unsigned int arg1,
2892 unsigned int arg2)
2893 {
2894 /*
2895 * Sleep.
2896 *
2897 * This is device specific and should be overridden by sub-class.
2898 *
2899 * Opcode : 1001 0101 1000 1000
2900 * Usage : SLEEP
2901 * Operation : (see specific hardware specification for Sleep)
2902 * Flags : None
2903 * Num Clocks : 1
2904 */
2905 MCUCR *mcucr = (MCUCR *)avr_core_get_vdev_by_name (core, "MCUCR");
2906
2907 if (mcucr == NULL)
2908 avr_error ("MCUCR register not installed");
2909
2910 /* See if sleep mode is enabled */
2911 if (mcucr_get_bit (mcucr, bit_SE))
2912 {
2913 if (mcucr_get_bit (mcucr, bit_SM) == 0)
2914 {
2915 /* Idle Mode */
2916 avr_core_set_sleep_mode (core, SLEEP_MODE_IDLE);
2917 }
2918 else
2919 {
2920 /* Power Down Mode */
2921 avr_core_set_sleep_mode (core, SLEEP_MODE_PWR_DOWN);
2922 }
2923 }
2924
2925 avr_core_PC_incr (core, 1);
2926 avr_core_inst_CKS_set (core, 1);
2927
2928 return opcode_SLEEP;
2929 }
2930
2931 static int
2932 avr_op_SPM (AvrCore *core, uint16_t opcode, unsigned int arg1,
2933 unsigned int arg2)
2934 {
2935 /*
2936 * Store Program Memory.
2937 *
2938 * Opcode : 1001 0101 1110 1000
2939 * Usage : SPM
2940 * Operation : (Z) <- R1:R0
2941 * Flags : None
2942 * Num Clocks : -
2943 */
2944 avr_error ("This opcode is not implemented yet: 0x%04x", opcode);
2945 return opcode_SPM;
2946 }
2947
2948 static int
2949 avr_op_STD_Y (AvrCore *core, uint16_t opcode, unsigned int arg1,
2950 unsigned int arg2)
2951 {
2952 /*
2953 * Store Indirect with Displacement.
2954 *
2955 * Opcode : 10q0 qq1d dddd 1qqq
2956 * Usage : STD Y+q, Rd
2957 * Operation : (Y + q) <- Rd
2958 * Flags : None
2959 * Num Clocks : 2
2960 */
2961 int Y;
2962
2963 int q = arg2;
2964 int Rd = arg1;
2965
2966 /* Y is R29:R28 */
2967 Y = (avr_core_gpwr_get (core, 29) << 8) + avr_core_gpwr_get (core, 28);
2968
2969 avr_core_mem_write (core, Y + q, avr_core_gpwr_get (core, Rd));
2970
2971 avr_core_PC_incr (core, 1);
2972 avr_core_inst_CKS_set (core, 2);
2973
2974 return opcode_STD_Y;
2975 }
2976
2977 static int
2978 avr_op_STD_Z (AvrCore *core, uint16_t opcode, unsigned int arg1,
2979 unsigned int arg2)
2980 {
2981 /*
2982 * Store Indirect with Displacement.
2983 *
2984 * Opcode : 10q0 qq1d dddd 0qqq
2985 * Usage : STD Z+q, Rd
2986 * Operation : (Z + q) <- Rd
2987 * Flags : None
2988 * Num Clocks : 2
2989 */
2990 int Z;
2991
2992 int q = arg2;
2993 int Rd = arg1;
2994
2995 /* Z is R31:R30 */
2996 Z = (avr_core_gpwr_get (core, 31) << 8) + avr_core_gpwr_get (core, 30);
2997
2998 avr_core_mem_write (core, Z + q, avr_core_gpwr_get (core, Rd));
2999
3000 avr_core_PC_incr (core, 1);
3001 avr_core_inst_CKS_set (core, 2);
3002
3003 return opcode_STD_Z;
3004 }
3005
3006 static int
3007 avr_op_STS (AvrCore *core, uint16_t opcode, unsigned int arg1,
3008 unsigned int arg2)
3009 {
3010 /*
3011 * Store Direct to data space.
3012 *
3013 * Opcode : 1001 001d dddd 0000 kkkk kkkk kkkk kkkk
3014 * Usage : STS k, Rd
3015 * Operation : (k) <- Rd
3016 * Flags : None
3017 * Num Clocks : 2
3018 */
3019 int Rd = arg1;
3020
3021 /* Get data at k in current data segment and put into Rd */
3022 int k_pc = avr_core_PC_get (core) + 1;
3023 int k = flash_read (core->flash, k_pc);
3024
3025 avr_core_mem_write (core, k, avr_core_gpwr_get (core, Rd));
3026
3027 avr_core_PC_incr (core, 2);
3028 avr_core_inst_CKS_set (core, 2);
3029
3030 return opcode_STS;
3031 }
3032
3033 static int
3034 avr_op_ST_X (AvrCore *core, uint16_t opcode, unsigned int arg1,
3035 unsigned int arg2)
3036 {
3037 /*
3038 * Store Indirect using index X.
3039 *
3040 * Opcode : 1001 001d dddd 1100
3041 * Usage : ST X, Rd
3042 * Operation : (X) <- Rd
3043 * Flags : None
3044 * Num Clocks : 2
3045 */
3046 uint16_t X;
3047
3048 int Rd = arg1;
3049
3050 /* X is R27:R26 */
3051 X = (avr_core_gpwr_get (core, 27) << 8) + avr_core_gpwr_get (core, 26);
3052
3053 avr_core_mem_write (core, X, avr_core_gpwr_get (core, Rd));
3054
3055 avr_core_PC_incr (core, 1);
3056 avr_core_inst_CKS_set (core, 2);
3057
3058 return opcode_ST_X;
3059 }
3060
3061 static int
3062 avr_op_ST_X_decr (AvrCore *core, uint16_t opcode, unsigned int arg1,
3063 unsigned int arg2)
3064 {
3065 /*
3066 * Store Indirect and Pre-Decrement using index X.
3067 *
3068 * Opcode : 1001 001d dddd 1110
3069 * Usage : ST -X, Rd
3070 * Operation : X <- X - 1, (X) <- Rd
3071 * Flags : None
3072 * Num Clocks : 2
3073 */
3074 uint16_t X;
3075
3076 int Rd = arg1;
3077
3078 if ((Rd == 26) || (Rd == 27))
3079 avr_error ("Results of operation are undefined: 0x%04x", opcode);
3080
3081 /* X is R27:R26 */
3082 X = (avr_core_gpwr_get (core, 27) << 8) + avr_core_gpwr_get (core, 26);
3083
3084 /* Perform pre-decrement */
3085 X -= 1;
3086 avr_core_gpwr_set (core, 26, X & 0xff);
3087 avr_core_gpwr_set (core, 27, X >> 8);
3088
3089 avr_core_mem_write (core, X, avr_core_gpwr_get (core, Rd));
3090
3091 avr_core_PC_incr (core, 1);
3092 avr_core_inst_CKS_set (core, 2);
3093
3094 return opcode_ST_X_decr;
3095 }
3096
3097 static int
3098 avr_op_ST_X_incr (AvrCore *core, uint16_t opcode, unsigned int arg1,
3099 unsigned int arg2)
3100 {
3101 /*
3102 * Store Indirect and Post-Increment using index X.
3103 *
3104 * Opcode : 1001 001d dddd 1101
3105 * Usage : ST X+, Rd
3106 * Operation : (X) <- Rd, X <- X + 1
3107 * Flags : None
3108 * Num Clocks : 2
3109 */
3110 uint16_t X;
3111
3112 int Rd = arg1;
3113
3114 if ((Rd == 26) || (Rd == 27))
3115 avr_error ("Results of operation are undefined: 0x%04x", opcode);
3116
3117 /* X is R27:R26 */
3118 X = (avr_core_gpwr_get (core, 27) << 8) + avr_core_gpwr_get (core, 26);
3119
3120 avr_core_mem_write (core, X, avr_core_gpwr_get (core, Rd));
3121
3122 /* Perform post-increment */
3123 X += 1;
3124 avr_core_gpwr_set (core, 26, X & 0xff);
3125 avr_core_gpwr_set (core, 27, X >> 8);
3126
3127 avr_core_PC_incr (core, 1);
3128 avr_core_inst_CKS_set (core, 2);
3129
3130 return opcode_ST_X_incr;
3131 }
3132
3133 static int
3134 avr_op_ST_Y_decr (AvrCore *core, uint16_t opcode, unsigned int arg1,
3135 unsigned int arg2)
3136 {
3137 /*
3138 * Store Indirect and Pre-Decrement using index Y.
3139 *
3140 * Opcode : 1001 001d dddd 1010
3141 * Usage : ST -Y, Rd
3142 * Operation : Y <- Y - 1, (Y) <- Rd
3143 * Flags : None
3144 * Num Clocks : 2
3145 */
3146 uint16_t Y;
3147
3148 int Rd = arg1;
3149
3150 if ((Rd == 28) || (Rd == 29))
3151 avr_error ("Results of operation are undefined: 0x%04x", opcode);
3152
3153 /* Y is R29:R28 */
3154 Y = (avr_core_gpwr_get (core, 29) << 8) + avr_core_gpwr_get (core, 28);
3155
3156 /* Perform pre-decrement */
3157 Y -= 1;
3158 avr_core_gpwr_set (core, 28, Y & 0xff);
3159 avr_core_gpwr_set (core, 29, Y >> 8);
3160
3161 avr_core_mem_write (core, Y, avr_core_gpwr_get (core, Rd));
3162
3163 avr_core_PC_incr (core, 1);
3164 avr_core_inst_CKS_set (core, 2);
3165
3166 return opcode_ST_Y_decr;
3167 }
3168
3169 static int
3170 avr_op_ST_Y_incr (AvrCore *core, uint16_t opcode, unsigned int arg1,
3171 unsigned int arg2)
3172 {
3173 /*
3174 * Store Indirect and Post-Increment using index Y.
3175 *
3176 * Opcode : 1001 001d dddd 1001
3177 * Usage : ST Y+, Rd
3178 * Operation : (Y) <- Rd, Y <- Y + 1
3179 * Flags : None
3180 * Num Clocks : 2
3181 */
3182 uint16_t Y;
3183
3184 int Rd = arg1;
3185
3186 if ((Rd == 28) || (Rd == 29))
3187 avr_error ("Results of operation are undefined: 0x%04x", opcode);
3188
3189 /* Y is R29:R28 */
3190 Y = (avr_core_gpwr_get (core, 29) << 8) + avr_core_gpwr_get (core, 28);
3191
3192 avr_core_mem_write (core, Y, avr_core_gpwr_get (core, Rd));
3193
3194 /* Perform post-increment */
3195 Y += 1;
3196 avr_core_gpwr_set (core, 28, Y & 0xff);
3197 avr_core_gpwr_set (core, 29, Y >> 8);
3198
3199 avr_core_PC_incr (core, 1);
3200 avr_core_inst_CKS_set (core, 2);
3201
3202 return opcode_ST_Y_incr;
3203 }
3204
3205 static int
3206 avr_op_ST_Z_decr (AvrCore *core, uint16_t opcode, unsigned int arg1,
3207 unsigned int arg2)
3208 {
3209 /*
3210 * Store Indirect and Pre-Decrement using index Z.
3211 *
3212 * Opcode : 1001 001d dddd 0010
3213 * Usage : ST -Z, Rd
3214 * Operation : Z <- Z - 1, (Z) <- Rd
3215 * Flags : None
3216 * Num Clocks : 2
3217 */
3218 uint16_t Z;
3219
3220 int Rd = arg1;
3221
3222 if ((Rd == 30) || (Rd == 31))
3223 avr_error ("Results of operation are undefined: 0x%04x", opcode);
3224
3225 /* Z is R31:R30 */
3226 Z = (avr_core_gpwr_get (core, 31) << 8) + avr_core_gpwr_get (core, 30);
3227
3228 /* Perform pre-decrement */
3229 Z -= 1;
3230 avr_core_gpwr_set (core, 30, Z & 0xff);
3231 avr_core_gpwr_set (core, 31, Z >> 8);
3232
3233 avr_core_mem_write (core, Z, avr_core_gpwr_get (core, Rd));
3234
3235 avr_core_PC_incr (core, 1);
3236 avr_core_inst_CKS_set (core, 2);
3237
3238 return opcode_ST_Z_decr;
3239 }
3240
3241 static int
3242 avr_op_ST_Z_incr (AvrCore *core, uint16_t opcode, unsigned int arg1,
3243 unsigned int arg2)
3244 {
3245 /*
3246 * Store Indirect and Post-Increment using index Z.
3247 *
3248 * Opcode : 1001 001d dddd 0001
3249 * Usage : ST Z+, Rd
3250 * Operation : (Z) <- Rd, Z <- Z + 1
3251 * Flags : None
3252 * Num Clocks : 2
3253 */
3254 uint16_t Z;
3255
3256 int Rd = arg1;
3257
3258 if ((Rd == 30) || (Rd == 31))
3259 avr_error ("Results of operation are undefined: 0x%04x", opcode);
3260
3261 /* Z is R31:R30 */
3262 Z = (avr_core_gpwr_get (core, 31) << 8) + avr_core_gpwr_get (core, 30);
3263
3264 avr_core_mem_write (core, Z, avr_core_gpwr_get (core, Rd));
3265
3266 /* Perform post-increment */
3267 Z += 1;
3268 avr_core_gpwr_set (core, 30, Z & 0xff);
3269 avr_core_gpwr_set (core, 31, Z >> 8);
3270
3271 avr_core_PC_incr (core, 1);
3272 avr_core_inst_CKS_set (core, 2);
3273
3274 return opcode_ST_Z_incr;
3275 }
3276
3277 static int
3278 avr_op_SUB (AvrCore *core, uint16_t opcode, unsigned int arg1,
3279 unsigned int arg2)
3280 {
3281 /*
3282 * Subtract without Carry.
3283 *
3284 * Opcode : 0001 10rd dddd rrrr
3285 * Usage : SUB Rd, Rr
3286 * Operation : Rd <- Rd - Rr
3287 * Flags : Z,C,N,V,S,H
3288 * Num Clocks : 1
3289 */
3290 int Z, C, N, V, S, H;
3291
3292 int Rd = arg1;
3293 int Rr = arg2;
3294
3295 uint8_t rd = avr_core_gpwr_get (core, Rd);
3296 uint8_t rr = avr_core_gpwr_get (core, Rr);
3297
3298 uint8_t res = rd - rr;
3299
3300 uint8_t sreg = avr_core_sreg_get (core);
3301
3302 sreg = set_bit_in_byte (sreg, SREG_H, H =
3303 (get_sub_carry (res, rd, rr, 3)));
3304 sreg = set_bit_in_byte (sreg, SREG_V, V =
3305 (get_sub_overflow (res, rd, rr)));
3306 sreg = set_bit_in_byte (sreg, SREG_N, N = ((res >> 7) & 0x1));
3307 sreg = set_bit_in_byte (sreg, SREG_S, S = (N ^ V));
3308 sreg = set_bit_in_byte (sreg, SREG_Z, Z = ((res & 0xff) == 0));
3309 sreg = set_bit_in_byte (sreg, SREG_C, C =
3310 (get_sub_carry (res, rd, rr, 7)));
3311
3312 avr_core_sreg_set (core, sreg);
3313
3314 avr_core_gpwr_set (core, Rd, res);
3315
3316 avr_core_PC_incr (core, 1);
3317 avr_core_inst_CKS_set (core, 1);
3318
3319 return opcode_SUB;
3320 }
3321
3322 static int
3323 avr_op_SUBI (AvrCore *core, uint16_t opcode, unsigned int arg1,
3324 unsigned int arg2)
3325 {
3326 /*
3327 * Subtract Immediate.
3328 *
3329 * Opcode : 0101 KKKK dddd KKKK
3330 * Usage : SUBI Rd, K
3331 * Operation : Rd <- Rd - K
3332 * Flags : Z,C,N,V,S,H
3333 * Num Clocks : 1
3334 */
3335 int Z, C, N, V, S, H;
3336
3337 int Rd = arg1;
3338 uint8_t K = arg2;
3339
3340 uint8_t rd = avr_core_gpwr_get (core, Rd);
3341
3342 uint8_t res = rd - K;
3343
3344 uint8_t sreg = avr_core_sreg_get (core);
3345
3346 sreg = set_bit_in_byte (sreg, SREG_H, H =
3347 (get_sub_carry (res, rd, K, 3)));
3348 sreg = set_bit_in_byte (sreg, SREG_V, V =
3349 (get_sub_overflow (res, rd, K)));
3350 sreg = set_bit_in_byte (sreg, SREG_N, N = ((res >> 7) & 0x1));
3351 sreg = set_bit_in_byte (sreg, SREG_S, S = (N ^ V));
3352 sreg = set_bit_in_byte (sreg, SREG_Z, Z = ((res & 0xff) == 0));
3353 sreg = set_bit_in_byte (sreg, SREG_C, C =
3354 (get_sub_carry (res, rd, K, 7)));
3355
3356 avr_core_sreg_set (core, sreg);
3357
3358 avr_core_gpwr_set (core, Rd, res);
3359
3360 avr_core_PC_incr (core, 1);
3361 avr_core_inst_CKS_set (core, 1);
3362
3363 return opcode_SUBI;
3364 }
3365
3366 static int
3367 avr_op_SWAP (AvrCore *core, uint16_t opcode, unsigned int arg1,
3368 unsigned int arg2)
3369 {
3370 /*
3371 * Swap Nibbles.
3372 *
3373 * Opcode : 1001 010d dddd 0010
3374 * Usage : SWAP Rd
3375 * Operation : Rd(3..0) <--> Rd(7..4)
3376 * Flags : None
3377 * Num Clocks : 1
3378 */
3379 int Rd = arg1;
3380 uint8_t rd = avr_core_gpwr_get (core, Rd);
3381
3382 avr_core_gpwr_set (core, Rd, ((rd << 4) & 0xf0) | ((rd >> 4) & 0x0f));
3383
3384 avr_core_PC_incr (core, 1);
3385 avr_core_inst_CKS_set (core, 1);
3386
3387 return opcode_SWAP;
3388 }
3389
3390 static int
3391 avr_op_WDR (AvrCore *core, uint16_t opcode, unsigned int arg1,
3392 unsigned int arg2)
3393 {
3394 /*
3395 * Watchdog Reset.
3396 *
3397 * This is device specific and must be overridden by sub-class.
3398 *
3399 * Opcode : 1001 0101 1010 1000
3400 * Usage : WDR
3401 * Operation : (see specific hardware specification for WDR)
3402 * Flags : None
3403 * Num Clocks : 1
3404 */
3405 WDTCR *wdtcr = (WDTCR *)avr_core_get_vdev_by_name (core, "WDTCR");
3406
3407 if (wdtcr == NULL)
3408 avr_error ("Core device doesn't have WDTCR attached");
3409
3410 wdtcr_update (wdtcr);
3411
3412 avr_core_PC_incr (core, 1);
3413 avr_core_inst_CKS_set (core, 1);
3414
3415 return opcode_WDR;
3416 }
3417
3418 int
3419 avr_op_UNKNOWN (AvrCore *core, uint16_t opcode, unsigned int arg1,
3420 unsigned int arg2)
3421 {
3422 /*
3423 * An unknown opcode was seen. Treat it as a NOP, but return the UNKNOWN
3424 * so that the main loop can issue a warning.
3425 */
3426 avr_op_NOP (core, opcode, arg1, arg2);
3427 return opcode_UNKNOWN;
3428 }
3429
3430 /******************************************************************************\
3431 *
3432 * Decode an opcode into the opcode handler function.
3433 *
3434 * Generates a warning and returns NULL if opcode is invalid.
3435 *
3436 * Returns a pointer to the function to handle the opcode.
3437 *
3438 \******************************************************************************/
3439
3440 static void
3441 lookup_opcode (uint16_t opcode, struct opcode_info *opi)
3442 {
3443 uint16_t decode;
3444
3445 opi->arg1 = -1;
3446 opi->arg2 = -1;
3447 switch (opcode)
3448 {
3449 /* opcodes with no operands */
3450 case 0x9598:
3451 opi->func = avr_op_BREAK;
3452 return; /* 1001 0101 1001 1000 | BREAK */
3453 case 0x9519:
3454 opi->func = avr_op_EICALL;
3455 return; /* 1001 0101 0001 1001 | EICALL */
3456 case 0x9419:
3457 opi->func = avr_op_EIJMP;
3458 return; /* 1001 0100 0001 1001 | EIJMP */
3459 case 0x95D8:
3460 opi->func = avr_op_ELPM;
3461 return; /* 1001 0101 1101 1000 | ELPM */
3462 case 0x95F8:
3463 opi->func = avr_op_ESPM;
3464 return; /* 1001 0101 1111 1000 | ESPM */
3465 case 0x9509:
3466 opi->func = avr_op_ICALL;
3467 return; /* 1001 0101 0000 1001 | ICALL */
3468 case 0x9409:
3469 opi->func = avr_op_IJMP;
3470 return; /* 1001 0100 0000 1001 | IJMP */
3471 case 0x95C8:
3472 opi->func = avr_op_LPM;
3473 return; /* 1001 0101 1100 1000 | LPM */
3474 case 0x0000:
3475 opi->func = avr_op_NOP;
3476 return; /* 0000 0000 0000 0000 | NOP */
3477 case 0x9508:
3478 opi->func = avr_op_RET;
3479 return; /* 1001 0101 0000 1000 | RET */
3480 case 0x9518:
3481 opi->func = avr_op_RETI;
3482 return; /* 1001 0101 0001 1000 | RETI */
3483 case 0x9588:
3484 opi->func = avr_op_SLEEP;
3485 return; /* 1001 0101 1000 1000 | SLEEP */
3486 case 0x95E8:
3487 opi->func = avr_op_SPM;
3488 return; /* 1001 0101 1110 1000 | SPM */
3489 case 0x95A8:
3490 opi->func = avr_op_WDR;
3491 return; /* 1001 0101 1010 1000 | WDR */
3492
3493 default:
3494 {
3495 /* opcodes with two 5-bit register (Rd and Rr) operands */
3496 decode = opcode & ~(mask_Rd_5 | mask_Rr_5);
3497 opi->arg1 = get_rd_5 (opcode);
3498 opi->arg2 = get_rr_5 (opcode);
3499 switch (decode)
3500 {
3501 case 0x1C00:
3502 opi->func = avr_op_ADC;
3503 return; /* 0001 11rd dddd rrrr | ADC or ROL */
3504 case 0x0C00:
3505 opi->func = avr_op_ADD;
3506 return; /* 0000 11rd dddd rrrr | ADD or LSL */
3507 case 0x2000:
3508 opi->func = avr_op_AND;
3509 return; /* 0010 00rd dddd rrrr | AND or TST */
3510 case 0x1400:
3511 opi->func = avr_op_CP;
3512 return; /* 0001 01rd dddd rrrr | CP */
3513 case 0x0400:
3514 opi->func = avr_op_CPC;
3515 return; /* 0000 01rd dddd rrrr | CPC */
3516 case 0x1000:
3517 opi->func = avr_op_CPSE;
3518 return; /* 0001 00rd dddd rrrr | CPSE */
3519 case 0x2400:
3520 opi->func = avr_op_EOR;
3521 return; /* 0010 01rd dddd rrrr | EOR or CLR */
3522 case 0x2C00:
3523 opi->func = avr_op_MOV;
3524 return; /* 0010 11rd dddd rrrr | MOV */
3525 case 0x9C00:
3526 opi->func = avr_op_MUL;
3527 return; /* 1001 11rd dddd rrrr | MUL */
3528 case 0x2800:
3529 opi->func = avr_op_OR;
3530 return; /* 0010 10rd dddd rrrr | OR */
3531 case 0x0800:
3532 opi->func = avr_op_SBC;
3533 return; /* 0000 10rd dddd rrrr | SBC */
3534 case 0x1800:
3535 opi->func = avr_op_SUB;
3536 return; /* 0001 10rd dddd rrrr | SUB */
3537 }
3538
3539 /* opcode with a single register (Rd) as operand */
3540 decode = opcode & ~(mask_Rd_5);
3541 opi->arg1 = get_rd_5 (opcode);
3542 opi->arg2 = -1;
3543 switch (decode)
3544 {
3545 case 0x9405:
3546 opi->func = avr_op_ASR;
3547 return; /* 1001 010d dddd 0101 | ASR */
3548 case 0x9400:
3549 opi->func = avr_op_COM;
3550 return; /* 1001 010d dddd 0000 | COM */
3551 case 0x940A:
3552 opi->func = avr_op_DEC;
3553 return; /* 1001 010d dddd 1010 | DEC */
3554 case 0x9006:
3555 opi->func = avr_op_ELPM_Z;
3556 return; /* 1001 000d dddd 0110 | ELPM */
3557 case 0x9007:
3558 opi->func = avr_op_ELPM_Z_incr;
3559 return; /* 1001 000d dddd 0111 | ELPM */
3560 case 0x9403:
3561 opi->func = avr_op_INC;
3562 return; /* 1001 010d dddd 0011 | INC */
3563 case 0x9000:
3564 opi->func = avr_op_LDS;
3565 return; /* 1001 000d dddd 0000 | LDS */
3566 case 0x900C:
3567 opi->func = avr_op_LD_X;
3568 return; /* 1001 000d dddd 1100 | LD */
3569 case 0x900E:
3570 opi->func = avr_op_LD_X_decr;
3571 return; /* 1001 000d dddd 1110 | LD */
3572 case 0x900D:
3573 opi->func = avr_op_LD_X_incr;
3574 return; /* 1001 000d dddd 1101 | LD */
3575 case 0x900A:
3576 opi->func = avr_op_LD_Y_decr;
3577 return; /* 1001 000d dddd 1010 | LD */
3578 case 0x9009:
3579 opi->func = avr_op_LD_Y_incr;
3580 return; /* 1001 000d dddd 1001 | LD */
3581 case 0x9002:
3582 opi->func = avr_op_LD_Z_decr;
3583 return; /* 1001 000d dddd 0010 | LD */
3584 case 0x9001:
3585 opi->func = avr_op_LD_Z_incr;
3586 return; /* 1001 000d dddd 0001 | LD */
3587 case 0x9004:
3588 opi->func = avr_op_LPM_Z;
3589 return; /* 1001 000d dddd 0100 | LPM */
3590 case 0x9005:
3591 opi->func = avr_op_LPM_Z_incr;
3592 return; /* 1001 000d dddd 0101 | LPM */
3593 case 0x9406:
3594 opi->func = avr_op_LSR;
3595 return; /* 1001 010d dddd 0110 | LSR */
3596 case 0x9401:
3597 opi->func = avr_op_NEG;
3598 return; /* 1001 010d dddd 0001 | NEG */
3599 case 0x900F:
3600 opi->func = avr_op_POP;
3601 return; /* 1001 000d dddd 1111 | POP */
3602 case 0x920F:
3603 opi->func = avr_op_PUSH;
3604 return; /* 1001 001d dddd 1111 | PUSH */
3605 case 0x9407:
3606 opi->func = avr_op_ROR;
3607 return; /* 1001 010d dddd 0111 | ROR */
3608 case 0x9200:
3609 opi->func = avr_op_STS;
3610 return; /* 1001 001d dddd 0000 | STS */
3611 case 0x920C:
3612 opi->func = avr_op_ST_X;
3613 return; /* 1001 001d dddd 1100 | ST */
3614 case 0x920E:
3615 opi->func = avr_op_ST_X_decr;
3616 return; /* 1001 001d dddd 1110 | ST */
3617 case 0x920D:
3618 opi->func = avr_op_ST_X_incr;
3619 return; /* 1001 001d dddd 1101 | ST */
3620 case 0x920A:
3621 opi->func = avr_op_ST_Y_decr;
3622 return; /* 1001 001d dddd 1010 | ST */
3623 case 0x9209:
3624 opi->func = avr_op_ST_Y_incr;
3625 return; /* 1001 001d dddd 1001 | ST */
3626 case 0x9202:
3627 opi->func = avr_op_ST_Z_decr;
3628 return; /* 1001 001d dddd 0010 | ST */
3629 case 0x9201:
3630 opi->func = avr_op_ST_Z_incr;
3631 return; /* 1001 001d dddd 0001 | ST */
3632 case 0x9402:
3633 opi->func = avr_op_SWAP;
3634 return; /* 1001 010d dddd 0010 | SWAP */
3635 }
3636
3637 /* opcodes with a register (Rd) and a constant data (K) as
3638 operands */
3639 decode = opcode & ~(mask_Rd_4 | mask_K_8);
3640 opi->arg1 = get_rd_4 (opcode);
3641 opi->arg2 = get_K_8 (opcode);
3642 switch (decode)
3643 {
3644 case 0x7000:
3645 opi->func = avr_op_ANDI;
3646 return; /* 0111 KKKK dddd KKKK | CBR or ANDI */
3647 case 0x3000:
3648 opi->func = avr_op_CPI;
3649 return; /* 0011 KKKK dddd KKKK | CPI */
3650 case 0xE000:
3651 opi->func = avr_op_LDI;
3652 return; /* 1110 KKKK dddd KKKK | LDI or SER */
3653 case 0x6000:
3654 opi->func = avr_op_ORI;
3655 return; /* 0110 KKKK dddd KKKK | SBR or ORI */
3656 case 0x4000:
3657 opi->func = avr_op_SBCI;
3658 return; /* 0100 KKKK dddd KKKK | SBCI */
3659 case 0x5000:
3660 opi->func = avr_op_SUBI;
3661 return; /* 0101 KKKK dddd KKKK | SUBI */
3662 }
3663
3664 /* opcodes with a register (Rd) and a register bit number (b)
3665 as operands */
3666 decode = opcode & ~(mask_Rd_5 | mask_reg_bit);
3667 opi->arg1 = get_rd_5 (opcode);
3668 opi->arg2 = get_reg_bit (opcode);
3669 switch (decode)
3670 {
3671 case 0xF800:
3672 opi->func = avr_op_BLD;
3673 return; /* 1111 100d dddd 0bbb | BLD */
3674 case 0xFA00:
3675 opi->func = avr_op_BST;
3676 return; /* 1111 101d dddd 0bbb | BST */
3677 case 0xFC00:
3678 opi->func = avr_op_SBRC;
3679 return; /* 1111 110d dddd 0bbb | SBRC */
3680 case 0xFE00:
3681 opi->func = avr_op_SBRS;
3682 return; /* 1111 111d dddd 0bbb | SBRS */
3683 }
3684
3685 /* opcodes with a relative 7-bit address (k) and a register
3686 bit number (b) as operands */
3687 decode = opcode & ~(mask_k_7 | mask_reg_bit);
3688 opi->arg1 = get_reg_bit (opcode);
3689 opi->arg2 = n_bit_unsigned_to_signed (get_k_7 (opcode), 7);
3690 switch (decode)
3691 {
3692 case 0xF400:
3693 opi->func = avr_op_BRBC;
3694 return; /* 1111 01kk kkkk kbbb | BRBC */
3695 case 0xF000:
3696 opi->func = avr_op_BRBS;
3697 return; /* 1111 00kk kkkk kbbb | BRBS */
3698 }
3699
3700 /* opcodes with a 6-bit address displacement (q) and a
3701 register (Rd) as operands */
3702 decode = opcode & ~(mask_Rd_5 | mask_q_displ);
3703 opi->arg1 = get_rd_5 (opcode);
3704 opi->arg2 = get_q (opcode);
3705 switch (decode)
3706 {
3707 case 0x8008:
3708 opi->func = avr_op_LDD_Y;
3709 return; /* 10q0 qq0d dddd 1qqq | LDD */
3710 case 0x8000:
3711 opi->func = avr_op_LDD_Z;
3712 return; /* 10q0 qq0d dddd 0qqq | LDD */
3713 case 0x8208:
3714 opi->func = avr_op_STD_Y;
3715 return; /* 10q0 qq1d dddd 1qqq | STD */
3716 case 0x8200:
3717 opi->func = avr_op_STD_Z;
3718 return; /* 10q0 qq1d dddd 0qqq | STD */
3719 }
3720
3721 /* opcodes with a absolute 22-bit address (k) operand */
3722 decode = opcode & ~(mask_k_22);
3723 opi->arg1 = get_k_22 (opcode);
3724 opi->arg2 = -1;
3725 switch (decode)
3726 {
3727 case 0x940E:
3728 opi->func = avr_op_CALL;
3729 return; /* 1001 010k kkkk 111k | CALL */
3730 case 0x940C:
3731 opi->func = avr_op_JMP;
3732 return; /* 1001 010k kkkk 110k | JMP */
3733 }
3734
3735 /* opcode with a sreg bit select (s) operand */
3736 decode = opcode & ~(mask_sreg_bit);
3737 opi->arg1 = get_sreg_bit (opcode);
3738 opi->arg2 = -1;
3739 switch (decode)
3740 {
3741 /* BCLR takes place of CL{C,Z,N,V,S,H,T,I} */
3742 /* BSET takes place of SE{C,Z,N,V,S,H,T,I} */
3743 case 0x9488:
3744 opi->func = avr_op_BCLR;
3745 return; /* 1001 0100 1sss 1000 | BCLR */
3746 case 0x9408:
3747 opi->func = avr_op_BSET;
3748 return; /* 1001 0100 0sss 1000 | BSET */
3749 }
3750
3751 /* opcodes with a 6-bit constant (K) and a register (Rd) as
3752 operands */
3753 decode = opcode & ~(mask_K_6 | mask_Rd_2);
3754 opi->arg1 = get_rd_2 (opcode);
3755 opi->arg2 = get_K_6 (opcode);
3756 switch (decode)
3757 {
3758 case 0x9600:
3759 opi->func = avr_op_ADIW;
3760 return; /* 1001 0110 KKdd KKKK | ADIW */
3761 case 0x9700:
3762 opi->func = avr_op_SBIW;
3763 return; /* 1001 0111 KKdd KKKK | SBIW */
3764 }
3765
3766 /* opcodes with a 5-bit IO Addr (A) and register bit number
3767 (b) as operands */
3768 decode = opcode & ~(mask_A_5 | mask_reg_bit);
3769 opi->arg1 = get_A_5 (opcode);
3770 opi->arg2 = get_reg_bit (opcode);
3771 switch (decode)
3772 {
3773 case 0x9800:
3774 opi->func = avr_op_CBI;
3775 return; /* 1001 1000 AAAA Abbb | CBI */
3776 case 0x9A00:
3777 opi->func = avr_op_SBI;
3778 return; /* 1001 1010 AAAA Abbb | SBI */
3779 case 0x9900:
3780 opi->func = avr_op_SBIC;
3781 return; /* 1001 1001 AAAA Abbb | SBIC */
3782 case 0x9B00:
3783 opi->func = avr_op_SBIS;
3784 return; /* 1001 1011 AAAA Abbb | SBIS */
3785 }
3786
3787 /* opcodes with a 6-bit IO Addr (A) and register (Rd) as
3788 operands */
3789 decode = opcode & ~(mask_A_6 | mask_Rd_5);
3790 opi->arg1 = get_rd_5 (opcode);
3791 opi->arg2 = get_A_6 (opcode);
3792 switch (decode)
3793 {
3794 case 0xB000:
3795 opi->func = avr_op_IN;
3796 return; /* 1011 0AAd dddd AAAA | IN */
3797 case 0xB800:
3798 opi->func = avr_op_OUT;
3799 return; /* 1011 1AAd dddd AAAA | OUT */
3800 }
3801
3802 /* opcodes with a relative 12-bit address (k) operand */
3803 decode = opcode & ~(mask_k_12);
3804 opi->arg1 = n_bit_unsigned_to_signed (get_k_12 (opcode), 12);
3805 opi->arg2 = -1;
3806 switch (decode)
3807 {
3808 case 0xD000:
3809 opi->func = avr_op_RCALL;
3810 return; /* 1101 kkkk kkkk kkkk | RCALL */
3811 case 0xC000:
3812 opi->func = avr_op_RJMP;
3813 return; /* 1100 kkkk kkkk kkkk | RJMP */
3814 }
3815
3816 /* opcodes with two 4-bit register (Rd and Rr) operands */
3817 decode = opcode & ~(mask_Rd_4 | mask_Rr_4);
3818 opi->arg1 = get_rd_4 (opcode);
3819 opi->arg2 = get_rr_4 (opcode);
3820 switch (decode)
3821 {
3822 case 0x0100:
3823 opi->func = avr_op_MOVW;
3824 return; /* 0000 0001 dddd rrrr | MOVW */
3825 case 0x0200:
3826 opi->func = avr_op_MULS;
3827 return; /* 0000 0010 dddd rrrr | MULS */
3828 }
3829
3830 /* opcodes with two 3-bit register (Rd and Rr) operands */
3831 decode = opcode & ~(mask_Rd_3 | mask_Rr_3);
3832 opi->arg1 = get_rd_3 (opcode);
3833 opi->arg2 = get_rr_3 (opcode);
3834 switch (decode)
3835 {
3836 case 0x0300:
3837 opi->func = avr_op_MULSU;
3838 return; /* 0000 0011 0ddd 0rrr | MULSU */
3839 case 0x0308:
3840 opi->func = avr_op_FMUL;
3841 return; /* 0000 0011 0ddd 1rrr | FMUL */
3842 case 0x0380:
3843 opi->func = avr_op_FMULS;
3844 return; /* 0000 0011 1ddd 0rrr | FMULS */
3845 case 0x0388:
3846 opi->func = avr_op_FMULSU;
3847 return; /* 0000 0011 1ddd 1rrr | FMULSU */
3848 }
3849
3850 } /* default */
3851 } /* first switch */
3852
3853 opi->func = avr_op_UNKNOWN;
3854 opi->arg1 = -1;
3855 opi->arg2 = -1;
3856
3857 } /* decode opcode function */
3858
3859 /**
3860 * \brief Initialize the decoder lookup table.
3861 *
3862 * This is automatically called by avr_core_construct().
3863 *
3864 * It is safe to call this function many times, since if will only create the
3865 * table the first time it is called.
3866 */
3867
3868 void
3869 decode_init_lookup_table (void)
3870 {
3871 if (global_opcode_lookup_table == NULL)
3872 {
3873 int num_ops = 0x10000;
3874 int i;
3875 avr_message ("generating opcode lookup_table\n");
3876 global_opcode_lookup_table = avr_new0 (struct opcode_info, num_ops);
3877 for (i = 0; i < num_ops; i++)
3878 {
3879 lookup_opcode (i, global_opcode_lookup_table + i);
3880 }
3881 }
3882 }
3883
3884 /**
3885 * \brief Decode an opcode into the opcode handler function.
3886 *
3887 * Generates a warning and returns NULL if opcode is invalid.
3888 *
3889 * Returns a pointer to the function to handle the opcode.
3890 */
3891
3892 extern inline struct opcode_info *decode_opcode (uint16_t opcode);

Automatically generated by Doxygen 1.8.2 on Mon Aug 18 2014.