require '_h2ph_pre.ph';

no warnings 'redefine';

unless(defined(&__RADEON_DRM_H__)) {
    eval 'sub __RADEON_DRM_H__ () {1;}' unless defined(&__RADEON_DRM_H__);
    unless(defined(&__RADEON_SAREA_DEFINES__)) {
	eval 'sub __RADEON_SAREA_DEFINES__ () {1;}' unless defined(&__RADEON_SAREA_DEFINES__);
	eval 'sub RADEON_UPLOAD_CONTEXT () {0x1;}' unless defined(&RADEON_UPLOAD_CONTEXT);
	eval 'sub RADEON_UPLOAD_VERTFMT () {0x2;}' unless defined(&RADEON_UPLOAD_VERTFMT);
	eval 'sub RADEON_UPLOAD_LINE () {0x4;}' unless defined(&RADEON_UPLOAD_LINE);
	eval 'sub RADEON_UPLOAD_BUMPMAP () {0x8;}' unless defined(&RADEON_UPLOAD_BUMPMAP);
	eval 'sub RADEON_UPLOAD_MASKS () {0x10;}' unless defined(&RADEON_UPLOAD_MASKS);
	eval 'sub RADEON_UPLOAD_VIEWPORT () {0x20;}' unless defined(&RADEON_UPLOAD_VIEWPORT);
	eval 'sub RADEON_UPLOAD_SETUP () {0x40;}' unless defined(&RADEON_UPLOAD_SETUP);
	eval 'sub RADEON_UPLOAD_TCL () {0x80;}' unless defined(&RADEON_UPLOAD_TCL);
	eval 'sub RADEON_UPLOAD_MISC () {0x100;}' unless defined(&RADEON_UPLOAD_MISC);
	eval 'sub RADEON_UPLOAD_TEX0 () {0x200;}' unless defined(&RADEON_UPLOAD_TEX0);
	eval 'sub RADEON_UPLOAD_TEX1 () {0x400;}' unless defined(&RADEON_UPLOAD_TEX1);
	eval 'sub RADEON_UPLOAD_TEX2 () {0x800;}' unless defined(&RADEON_UPLOAD_TEX2);
	eval 'sub RADEON_UPLOAD_TEX0IMAGES () {0x1000;}' unless defined(&RADEON_UPLOAD_TEX0IMAGES);
	eval 'sub RADEON_UPLOAD_TEX1IMAGES () {0x2000;}' unless defined(&RADEON_UPLOAD_TEX1IMAGES);
	eval 'sub RADEON_UPLOAD_TEX2IMAGES () {0x4000;}' unless defined(&RADEON_UPLOAD_TEX2IMAGES);
	eval 'sub RADEON_UPLOAD_CLIPRECTS () {0x8000;}' unless defined(&RADEON_UPLOAD_CLIPRECTS);
	eval 'sub RADEON_REQUIRE_QUIESCENCE () {0x10000;}' unless defined(&RADEON_REQUIRE_QUIESCENCE);
	eval 'sub RADEON_UPLOAD_ZBIAS () {0x20000;}' unless defined(&RADEON_UPLOAD_ZBIAS);
	eval 'sub RADEON_UPLOAD_ALL () {0x3effff;}' unless defined(&RADEON_UPLOAD_ALL);
	eval 'sub RADEON_UPLOAD_CONTEXT_ALL () {0x3e01ff;}' unless defined(&RADEON_UPLOAD_CONTEXT_ALL);
	eval 'sub RADEON_EMIT_PP_MISC () {0;}' unless defined(&RADEON_EMIT_PP_MISC);
	eval 'sub RADEON_EMIT_PP_CNTL () {1;}' unless defined(&RADEON_EMIT_PP_CNTL);
	eval 'sub RADEON_EMIT_RB3D_COLORPITCH () {2;}' unless defined(&RADEON_EMIT_RB3D_COLORPITCH);
	eval 'sub RADEON_EMIT_RE_LINE_PATTERN () {3;}' unless defined(&RADEON_EMIT_RE_LINE_PATTERN);
	eval 'sub RADEON_EMIT_SE_LINE_WIDTH () {4;}' unless defined(&RADEON_EMIT_SE_LINE_WIDTH);
	eval 'sub RADEON_EMIT_PP_LUM_MATRIX () {5;}' unless defined(&RADEON_EMIT_PP_LUM_MATRIX);
	eval 'sub RADEON_EMIT_PP_ROT_MATRIX_0 () {6;}' unless defined(&RADEON_EMIT_PP_ROT_MATRIX_0);
	eval 'sub RADEON_EMIT_RB3D_STENCILREFMASK () {7;}' unless defined(&RADEON_EMIT_RB3D_STENCILREFMASK);
	eval 'sub RADEON_EMIT_SE_VPORT_XSCALE () {8;}' unless defined(&RADEON_EMIT_SE_VPORT_XSCALE);
	eval 'sub RADEON_EMIT_SE_CNTL () {9;}' unless defined(&RADEON_EMIT_SE_CNTL);
	eval 'sub RADEON_EMIT_SE_CNTL_STATUS () {10;}' unless defined(&RADEON_EMIT_SE_CNTL_STATUS);
	eval 'sub RADEON_EMIT_RE_MISC () {11;}' unless defined(&RADEON_EMIT_RE_MISC);
	eval 'sub RADEON_EMIT_PP_TXFILTER_0 () {12;}' unless defined(&RADEON_EMIT_PP_TXFILTER_0);
	eval 'sub RADEON_EMIT_PP_BORDER_COLOR_0 () {13;}' unless defined(&RADEON_EMIT_PP_BORDER_COLOR_0);
	eval 'sub RADEON_EMIT_PP_TXFILTER_1 () {14;}' unless defined(&RADEON_EMIT_PP_TXFILTER_1);
	eval 'sub RADEON_EMIT_PP_BORDER_COLOR_1 () {15;}' unless defined(&RADEON_EMIT_PP_BORDER_COLOR_1);
	eval 'sub RADEON_EMIT_PP_TXFILTER_2 () {16;}' unless defined(&RADEON_EMIT_PP_TXFILTER_2);
	eval 'sub RADEON_EMIT_PP_BORDER_COLOR_2 () {17;}' unless defined(&RADEON_EMIT_PP_BORDER_COLOR_2);
	eval 'sub RADEON_EMIT_SE_ZBIAS_FACTOR () {18;}' unless defined(&RADEON_EMIT_SE_ZBIAS_FACTOR);
	eval 'sub RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT () {19;}' unless defined(&RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT);
	eval 'sub RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED () {20;}' unless defined(&RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED);
	eval 'sub R200_EMIT_PP_TXCBLEND_0 () {21;}' unless defined(&R200_EMIT_PP_TXCBLEND_0);
	eval 'sub R200_EMIT_PP_TXCBLEND_1 () {22;}' unless defined(&R200_EMIT_PP_TXCBLEND_1);
	eval 'sub R200_EMIT_PP_TXCBLEND_2 () {23;}' unless defined(&R200_EMIT_PP_TXCBLEND_2);
	eval 'sub R200_EMIT_PP_TXCBLEND_3 () {24;}' unless defined(&R200_EMIT_PP_TXCBLEND_3);
	eval 'sub R200_EMIT_PP_TXCBLEND_4 () {25;}' unless defined(&R200_EMIT_PP_TXCBLEND_4);
	eval 'sub R200_EMIT_PP_TXCBLEND_5 () {26;}' unless defined(&R200_EMIT_PP_TXCBLEND_5);
	eval 'sub R200_EMIT_PP_TXCBLEND_6 () {27;}' unless defined(&R200_EMIT_PP_TXCBLEND_6);
	eval 'sub R200_EMIT_PP_TXCBLEND_7 () {28;}' unless defined(&R200_EMIT_PP_TXCBLEND_7);
	eval 'sub R200_EMIT_TCL_LIGHT_MODEL_CTL_0 () {29;}' unless defined(&R200_EMIT_TCL_LIGHT_MODEL_CTL_0);
	eval 'sub R200_EMIT_TFACTOR_0 () {30;}' unless defined(&R200_EMIT_TFACTOR_0);
	eval 'sub R200_EMIT_VTX_FMT_0 () {31;}' unless defined(&R200_EMIT_VTX_FMT_0);
	eval 'sub R200_EMIT_VAP_CTL () {32;}' unless defined(&R200_EMIT_VAP_CTL);
	eval 'sub R200_EMIT_MATRIX_SELECT_0 () {33;}' unless defined(&R200_EMIT_MATRIX_SELECT_0);
	eval 'sub R200_EMIT_TEX_PROC_CTL_2 () {34;}' unless defined(&R200_EMIT_TEX_PROC_CTL_2);
	eval 'sub R200_EMIT_TCL_UCP_VERT_BLEND_CTL () {35;}' unless defined(&R200_EMIT_TCL_UCP_VERT_BLEND_CTL);
	eval 'sub R200_EMIT_PP_TXFILTER_0 () {36;}' unless defined(&R200_EMIT_PP_TXFILTER_0);
	eval 'sub R200_EMIT_PP_TXFILTER_1 () {37;}' unless defined(&R200_EMIT_PP_TXFILTER_1);
	eval 'sub R200_EMIT_PP_TXFILTER_2 () {38;}' unless defined(&R200_EMIT_PP_TXFILTER_2);
	eval 'sub R200_EMIT_PP_TXFILTER_3 () {39;}' unless defined(&R200_EMIT_PP_TXFILTER_3);
	eval 'sub R200_EMIT_PP_TXFILTER_4 () {40;}' unless defined(&R200_EMIT_PP_TXFILTER_4);
	eval 'sub R200_EMIT_PP_TXFILTER_5 () {41;}' unless defined(&R200_EMIT_PP_TXFILTER_5);
	eval 'sub R200_EMIT_PP_TXOFFSET_0 () {42;}' unless defined(&R200_EMIT_PP_TXOFFSET_0);
	eval 'sub R200_EMIT_PP_TXOFFSET_1 () {43;}' unless defined(&R200_EMIT_PP_TXOFFSET_1);
	eval 'sub R200_EMIT_PP_TXOFFSET_2 () {44;}' unless defined(&R200_EMIT_PP_TXOFFSET_2);
	eval 'sub R200_EMIT_PP_TXOFFSET_3 () {45;}' unless defined(&R200_EMIT_PP_TXOFFSET_3);
	eval 'sub R200_EMIT_PP_TXOFFSET_4 () {46;}' unless defined(&R200_EMIT_PP_TXOFFSET_4);
	eval 'sub R200_EMIT_PP_TXOFFSET_5 () {47;}' unless defined(&R200_EMIT_PP_TXOFFSET_5);
	eval 'sub R200_EMIT_VTE_CNTL () {48;}' unless defined(&R200_EMIT_VTE_CNTL);
	eval 'sub R200_EMIT_OUTPUT_VTX_COMP_SEL () {49;}' unless defined(&R200_EMIT_OUTPUT_VTX_COMP_SEL);
	eval 'sub R200_EMIT_PP_TAM_DEBUG3 () {50;}' unless defined(&R200_EMIT_PP_TAM_DEBUG3);
	eval 'sub R200_EMIT_PP_CNTL_X () {51;}' unless defined(&R200_EMIT_PP_CNTL_X);
	eval 'sub R200_EMIT_RB3D_DEPTHXY_OFFSET () {52;}' unless defined(&R200_EMIT_RB3D_DEPTHXY_OFFSET);
	eval 'sub R200_EMIT_RE_AUX_SCISSOR_CNTL () {53;}' unless defined(&R200_EMIT_RE_AUX_SCISSOR_CNTL);
	eval 'sub R200_EMIT_RE_SCISSOR_TL_0 () {54;}' unless defined(&R200_EMIT_RE_SCISSOR_TL_0);
	eval 'sub R200_EMIT_RE_SCISSOR_TL_1 () {55;}' unless defined(&R200_EMIT_RE_SCISSOR_TL_1);
	eval 'sub R200_EMIT_RE_SCISSOR_TL_2 () {56;}' unless defined(&R200_EMIT_RE_SCISSOR_TL_2);
	eval 'sub R200_EMIT_SE_VAP_CNTL_STATUS () {57;}' unless defined(&R200_EMIT_SE_VAP_CNTL_STATUS);
	eval 'sub R200_EMIT_SE_VTX_STATE_CNTL () {58;}' unless defined(&R200_EMIT_SE_VTX_STATE_CNTL);
	eval 'sub R200_EMIT_RE_POINTSIZE () {59;}' unless defined(&R200_EMIT_RE_POINTSIZE);
	eval 'sub R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0 () {60;}' unless defined(&R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0);
	eval 'sub R200_EMIT_PP_CUBIC_FACES_0 () {61;}' unless defined(&R200_EMIT_PP_CUBIC_FACES_0);
	eval 'sub R200_EMIT_PP_CUBIC_OFFSETS_0 () {62;}' unless defined(&R200_EMIT_PP_CUBIC_OFFSETS_0);
	eval 'sub R200_EMIT_PP_CUBIC_FACES_1 () {63;}' unless defined(&R200_EMIT_PP_CUBIC_FACES_1);
	eval 'sub R200_EMIT_PP_CUBIC_OFFSETS_1 () {64;}' unless defined(&R200_EMIT_PP_CUBIC_OFFSETS_1);
	eval 'sub R200_EMIT_PP_CUBIC_FACES_2 () {65;}' unless defined(&R200_EMIT_PP_CUBIC_FACES_2);
	eval 'sub R200_EMIT_PP_CUBIC_OFFSETS_2 () {66;}' unless defined(&R200_EMIT_PP_CUBIC_OFFSETS_2);
	eval 'sub R200_EMIT_PP_CUBIC_FACES_3 () {67;}' unless defined(&R200_EMIT_PP_CUBIC_FACES_3);
	eval 'sub R200_EMIT_PP_CUBIC_OFFSETS_3 () {68;}' unless defined(&R200_EMIT_PP_CUBIC_OFFSETS_3);
	eval 'sub R200_EMIT_PP_CUBIC_FACES_4 () {69;}' unless defined(&R200_EMIT_PP_CUBIC_FACES_4);
	eval 'sub R200_EMIT_PP_CUBIC_OFFSETS_4 () {70;}' unless defined(&R200_EMIT_PP_CUBIC_OFFSETS_4);
	eval 'sub R200_EMIT_PP_CUBIC_FACES_5 () {71;}' unless defined(&R200_EMIT_PP_CUBIC_FACES_5);
	eval 'sub R200_EMIT_PP_CUBIC_OFFSETS_5 () {72;}' unless defined(&R200_EMIT_PP_CUBIC_OFFSETS_5);
	eval 'sub RADEON_EMIT_PP_TEX_SIZE_0 () {73;}' unless defined(&RADEON_EMIT_PP_TEX_SIZE_0);
	eval 'sub RADEON_EMIT_PP_TEX_SIZE_1 () {74;}' unless defined(&RADEON_EMIT_PP_TEX_SIZE_1);
	eval 'sub RADEON_EMIT_PP_TEX_SIZE_2 () {75;}' unless defined(&RADEON_EMIT_PP_TEX_SIZE_2);
	eval 'sub R200_EMIT_RB3D_BLENDCOLOR () {76;}' unless defined(&R200_EMIT_RB3D_BLENDCOLOR);
	eval 'sub R200_EMIT_TCL_POINT_SPRITE_CNTL () {77;}' unless defined(&R200_EMIT_TCL_POINT_SPRITE_CNTL);
	eval 'sub RADEON_EMIT_PP_CUBIC_FACES_0 () {78;}' unless defined(&RADEON_EMIT_PP_CUBIC_FACES_0);
	eval 'sub RADEON_EMIT_PP_CUBIC_OFFSETS_T0 () {79;}' unless defined(&RADEON_EMIT_PP_CUBIC_OFFSETS_T0);
	eval 'sub RADEON_EMIT_PP_CUBIC_FACES_1 () {80;}' unless defined(&RADEON_EMIT_PP_CUBIC_FACES_1);
	eval 'sub RADEON_EMIT_PP_CUBIC_OFFSETS_T1 () {81;}' unless defined(&RADEON_EMIT_PP_CUBIC_OFFSETS_T1);
	eval 'sub RADEON_EMIT_PP_CUBIC_FACES_2 () {82;}' unless defined(&RADEON_EMIT_PP_CUBIC_FACES_2);
	eval 'sub RADEON_EMIT_PP_CUBIC_OFFSETS_T2 () {83;}' unless defined(&RADEON_EMIT_PP_CUBIC_OFFSETS_T2);
	eval 'sub R200_EMIT_PP_TRI_PERF_CNTL () {84;}' unless defined(&R200_EMIT_PP_TRI_PERF_CNTL);
	eval 'sub R200_EMIT_PP_AFS_0 () {85;}' unless defined(&R200_EMIT_PP_AFS_0);
	eval 'sub R200_EMIT_PP_AFS_1 () {86;}' unless defined(&R200_EMIT_PP_AFS_1);
	eval 'sub R200_EMIT_ATF_TFACTOR () {87;}' unless defined(&R200_EMIT_ATF_TFACTOR);
	eval 'sub R200_EMIT_PP_TXCTLALL_0 () {88;}' unless defined(&R200_EMIT_PP_TXCTLALL_0);
	eval 'sub R200_EMIT_PP_TXCTLALL_1 () {89;}' unless defined(&R200_EMIT_PP_TXCTLALL_1);
	eval 'sub R200_EMIT_PP_TXCTLALL_2 () {90;}' unless defined(&R200_EMIT_PP_TXCTLALL_2);
	eval 'sub R200_EMIT_PP_TXCTLALL_3 () {91;}' unless defined(&R200_EMIT_PP_TXCTLALL_3);
	eval 'sub R200_EMIT_PP_TXCTLALL_4 () {92;}' unless defined(&R200_EMIT_PP_TXCTLALL_4);
	eval 'sub R200_EMIT_PP_TXCTLALL_5 () {93;}' unless defined(&R200_EMIT_PP_TXCTLALL_5);
	eval 'sub R200_EMIT_VAP_PVS_CNTL () {94;}' unless defined(&R200_EMIT_VAP_PVS_CNTL);
	eval 'sub RADEON_MAX_STATE_PACKETS () {95;}' unless defined(&RADEON_MAX_STATE_PACKETS);
	eval 'sub RADEON_CMD_PACKET () {1;}' unless defined(&RADEON_CMD_PACKET);
	eval 'sub RADEON_CMD_SCALARS () {2;}' unless defined(&RADEON_CMD_SCALARS);
	eval 'sub RADEON_CMD_VECTORS () {3;}' unless defined(&RADEON_CMD_VECTORS);
	eval 'sub RADEON_CMD_DMA_DISCARD () {4;}' unless defined(&RADEON_CMD_DMA_DISCARD);
	eval 'sub RADEON_CMD_PACKET3 () {5;}' unless defined(&RADEON_CMD_PACKET3);
	eval 'sub RADEON_CMD_PACKET3_CLIP () {6;}' unless defined(&RADEON_CMD_PACKET3_CLIP);
	eval 'sub RADEON_CMD_SCALARS2 () {7;}' unless defined(&RADEON_CMD_SCALARS2);
	eval 'sub RADEON_CMD_WAIT () {8;}' unless defined(&RADEON_CMD_WAIT);
	eval 'sub RADEON_CMD_VECLINEAR () {9;}' unless defined(&RADEON_CMD_VECLINEAR);
	eval 'sub RADEON_WAIT_2D () {0x1;}' unless defined(&RADEON_WAIT_2D);
	eval 'sub RADEON_WAIT_3D () {0x2;}' unless defined(&RADEON_WAIT_3D);
	eval 'sub R300_CMD_PACKET3_CLEAR () {0;}' unless defined(&R300_CMD_PACKET3_CLEAR);
	eval 'sub R300_CMD_PACKET3_RAW () {1;}' unless defined(&R300_CMD_PACKET3_RAW);
	eval 'sub R300_CMD_PACKET0 () {1;}' unless defined(&R300_CMD_PACKET0);
	eval 'sub R300_CMD_VPU () {2;}' unless defined(&R300_CMD_VPU);
	eval 'sub R300_CMD_PACKET3 () {3;}' unless defined(&R300_CMD_PACKET3);
	eval 'sub R300_CMD_END3D () {4;}' unless defined(&R300_CMD_END3D);
	eval 'sub R300_CMD_CP_DELAY () {5;}' unless defined(&R300_CMD_CP_DELAY);
	eval 'sub R300_CMD_DMA_DISCARD () {6;}' unless defined(&R300_CMD_DMA_DISCARD);
	eval 'sub R300_CMD_WAIT () {7;}' unless defined(&R300_CMD_WAIT);
	eval 'sub R300_WAIT_2D () {0x1;}' unless defined(&R300_WAIT_2D);
	eval 'sub R300_WAIT_3D () {0x2;}' unless defined(&R300_WAIT_3D);
	eval 'sub R300_WAIT_2D_CLEAN () {0x3;}' unless defined(&R300_WAIT_2D_CLEAN);
	eval 'sub R300_WAIT_3D_CLEAN () {0x4;}' unless defined(&R300_WAIT_3D_CLEAN);
	eval 'sub R300_NEW_WAIT_2D_3D () {0x3;}' unless defined(&R300_NEW_WAIT_2D_3D);
	eval 'sub R300_NEW_WAIT_2D_2D_CLEAN () {0x4;}' unless defined(&R300_NEW_WAIT_2D_2D_CLEAN);
	eval 'sub R300_NEW_WAIT_3D_3D_CLEAN () {0x6;}' unless defined(&R300_NEW_WAIT_3D_3D_CLEAN);
	eval 'sub R300_NEW_WAIT_2D_2D_CLEAN_3D_3D_CLEAN () {0x8;}' unless defined(&R300_NEW_WAIT_2D_2D_CLEAN_3D_3D_CLEAN);
	eval 'sub R300_CMD_SCRATCH () {8;}' unless defined(&R300_CMD_SCRATCH);
	eval 'sub R300_CMD_R500FP () {9;}' unless defined(&R300_CMD_R500FP);
	eval 'sub RADEON_FRONT () {0x1;}' unless defined(&RADEON_FRONT);
	eval 'sub RADEON_BACK () {0x2;}' unless defined(&RADEON_BACK);
	eval 'sub RADEON_DEPTH () {0x4;}' unless defined(&RADEON_DEPTH);
	eval 'sub RADEON_STENCIL () {0x8;}' unless defined(&RADEON_STENCIL);
	eval 'sub RADEON_CLEAR_FASTZ () {0x80000000;}' unless defined(&RADEON_CLEAR_FASTZ);
	eval 'sub RADEON_USE_HIERZ () {0x40000000;}' unless defined(&RADEON_USE_HIERZ);
	eval 'sub RADEON_USE_COMP_ZBUF () {0x20000000;}' unless defined(&RADEON_USE_COMP_ZBUF);
	eval 'sub R500FP_CONSTANT_TYPE () {(1<< 1);}' unless defined(&R500FP_CONSTANT_TYPE);
	eval 'sub R500FP_CONSTANT_CLAMP () {(1<< 2);}' unless defined(&R500FP_CONSTANT_CLAMP);
	eval 'sub RADEON_POINTS () {0x1;}' unless defined(&RADEON_POINTS);
	eval 'sub RADEON_LINES () {0x2;}' unless defined(&RADEON_LINES);
	eval 'sub RADEON_LINE_STRIP () {0x3;}' unless defined(&RADEON_LINE_STRIP);
	eval 'sub RADEON_TRIANGLES () {0x4;}' unless defined(&RADEON_TRIANGLES);
	eval 'sub RADEON_TRIANGLE_FAN () {0x5;}' unless defined(&RADEON_TRIANGLE_FAN);
	eval 'sub RADEON_TRIANGLE_STRIP () {0x6;}' unless defined(&RADEON_TRIANGLE_STRIP);
	eval 'sub RADEON_BUFFER_SIZE () {65536;}' unless defined(&RADEON_BUFFER_SIZE);
	eval 'sub RADEON_INDEX_PRIM_OFFSET () {20;}' unless defined(&RADEON_INDEX_PRIM_OFFSET);
	eval 'sub RADEON_SCRATCH_REG_OFFSET () {32;}' unless defined(&RADEON_SCRATCH_REG_OFFSET);
	eval 'sub RADEON_NR_SAREA_CLIPRECTS () {12;}' unless defined(&RADEON_NR_SAREA_CLIPRECTS);
	eval 'sub RADEON_LOCAL_TEX_HEAP () {0;}' unless defined(&RADEON_LOCAL_TEX_HEAP);
	eval 'sub RADEON_GART_TEX_HEAP () {1;}' unless defined(&RADEON_GART_TEX_HEAP);
	eval 'sub RADEON_NR_TEX_HEAPS () {2;}' unless defined(&RADEON_NR_TEX_HEAPS);
	eval 'sub RADEON_NR_TEX_REGIONS () {64;}' unless defined(&RADEON_NR_TEX_REGIONS);
	eval 'sub RADEON_LOG_TEX_GRANULARITY () {16;}' unless defined(&RADEON_LOG_TEX_GRANULARITY);
	eval 'sub RADEON_MAX_TEXTURE_LEVELS () {12;}' unless defined(&RADEON_MAX_TEXTURE_LEVELS);
	eval 'sub RADEON_MAX_TEXTURE_UNITS () {3;}' unless defined(&RADEON_MAX_TEXTURE_UNITS);
	eval 'sub RADEON_MAX_SURFACES () {8;}' unless defined(&RADEON_MAX_SURFACES);
	eval 'sub RADEON_OFFSET_SHIFT () {10;}' unless defined(&RADEON_OFFSET_SHIFT);
	eval 'sub RADEON_OFFSET_ALIGN () {(1<<  &RADEON_OFFSET_SHIFT);}' unless defined(&RADEON_OFFSET_ALIGN);
	eval 'sub RADEON_OFFSET_MASK () {( &RADEON_OFFSET_ALIGN - 1);}' unless defined(&RADEON_OFFSET_MASK);
    }
    eval 'sub DRM_RADEON_CP_INIT () {0x;}' unless defined(&DRM_RADEON_CP_INIT);
    eval 'sub DRM_RADEON_CP_START () {0x1;}' unless defined(&DRM_RADEON_CP_START);
    eval 'sub DRM_RADEON_CP_STOP () {0x2;}' unless defined(&DRM_RADEON_CP_STOP);
    eval 'sub DRM_RADEON_CP_RESET () {0x3;}' unless defined(&DRM_RADEON_CP_RESET);
    eval 'sub DRM_RADEON_CP_IDLE () {0x4;}' unless defined(&DRM_RADEON_CP_IDLE);
    eval 'sub DRM_RADEON_RESET () {0x5;}' unless defined(&DRM_RADEON_RESET);
    eval 'sub DRM_RADEON_FULLSCREEN () {0x6;}' unless defined(&DRM_RADEON_FULLSCREEN);
    eval 'sub DRM_RADEON_SWAP () {0x7;}' unless defined(&DRM_RADEON_SWAP);
    eval 'sub DRM_RADEON_CLEAR () {0x8;}' unless defined(&DRM_RADEON_CLEAR);
    eval 'sub DRM_RADEON_VERTEX () {0x9;}' unless defined(&DRM_RADEON_VERTEX);
    eval 'sub DRM_RADEON_INDICES () {0xa;}' unless defined(&DRM_RADEON_INDICES);
    eval 'sub DRM_RADEON_NOT_USED () {1;}' unless defined(&DRM_RADEON_NOT_USED);
    eval 'sub DRM_RADEON_STIPPLE () {0xc;}' unless defined(&DRM_RADEON_STIPPLE);
    eval 'sub DRM_RADEON_INDIRECT () {0xd;}' unless defined(&DRM_RADEON_INDIRECT);
    eval 'sub DRM_RADEON_TEXTURE () {0xe;}' unless defined(&DRM_RADEON_TEXTURE);
    eval 'sub DRM_RADEON_VERTEX2 () {0xf;}' unless defined(&DRM_RADEON_VERTEX2);
    eval 'sub DRM_RADEON_CMDBUF () {0x10;}' unless defined(&DRM_RADEON_CMDBUF);
    eval 'sub DRM_RADEON_GETPARAM () {0x11;}' unless defined(&DRM_RADEON_GETPARAM);
    eval 'sub DRM_RADEON_FLIP () {0x12;}' unless defined(&DRM_RADEON_FLIP);
    eval 'sub DRM_RADEON_ALLOC () {0x13;}' unless defined(&DRM_RADEON_ALLOC);
    eval 'sub DRM_RADEON_FREE () {0x14;}' unless defined(&DRM_RADEON_FREE);
    eval 'sub DRM_RADEON_INIT_HEAP () {0x15;}' unless defined(&DRM_RADEON_INIT_HEAP);
    eval 'sub DRM_RADEON_IRQ_EMIT () {0x16;}' unless defined(&DRM_RADEON_IRQ_EMIT);
    eval 'sub DRM_RADEON_IRQ_WAIT () {0x17;}' unless defined(&DRM_RADEON_IRQ_WAIT);
    eval 'sub DRM_RADEON_CP_RESUME () {0x18;}' unless defined(&DRM_RADEON_CP_RESUME);
    eval 'sub DRM_RADEON_SETPARAM () {0x19;}' unless defined(&DRM_RADEON_SETPARAM);
    eval 'sub DRM_RADEON_SURF_ALLOC () {0x1a;}' unless defined(&DRM_RADEON_SURF_ALLOC);
    eval 'sub DRM_RADEON_SURF_FREE () {0x1b;}' unless defined(&DRM_RADEON_SURF_FREE);
    eval 'sub DRM_IOCTL_RADEON_CP_INIT () { &DRM_IOW(  &DRM_COMMAND_BASE +  &DRM_RADEON_CP_INIT,  &drm_radeon_init_t);}' unless defined(&DRM_IOCTL_RADEON_CP_INIT);
    eval 'sub DRM_IOCTL_RADEON_CP_START () { &DRM_IO(  &DRM_COMMAND_BASE +  &DRM_RADEON_CP_START);}' unless defined(&DRM_IOCTL_RADEON_CP_START);
    eval 'sub DRM_IOCTL_RADEON_CP_STOP () { &DRM_IOW(  &DRM_COMMAND_BASE +  &DRM_RADEON_CP_STOP,  &drm_radeon_cp_stop_t);}' unless defined(&DRM_IOCTL_RADEON_CP_STOP);
    eval 'sub DRM_IOCTL_RADEON_CP_RESET () { &DRM_IO(  &DRM_COMMAND_BASE +  &DRM_RADEON_CP_RESET);}' unless defined(&DRM_IOCTL_RADEON_CP_RESET);
    eval 'sub DRM_IOCTL_RADEON_CP_IDLE () { &DRM_IO(  &DRM_COMMAND_BASE +  &DRM_RADEON_CP_IDLE);}' unless defined(&DRM_IOCTL_RADEON_CP_IDLE);
    eval 'sub DRM_IOCTL_RADEON_RESET () { &DRM_IO(  &DRM_COMMAND_BASE +  &DRM_RADEON_RESET);}' unless defined(&DRM_IOCTL_RADEON_RESET);
    eval 'sub DRM_IOCTL_RADEON_FULLSCREEN () { &DRM_IOW(  &DRM_COMMAND_BASE +  &DRM_RADEON_FULLSCREEN,  &drm_radeon_fullscreen_t);}' unless defined(&DRM_IOCTL_RADEON_FULLSCREEN);
    eval 'sub DRM_IOCTL_RADEON_SWAP () { &DRM_IO(  &DRM_COMMAND_BASE +  &DRM_RADEON_SWAP);}' unless defined(&DRM_IOCTL_RADEON_SWAP);
    eval 'sub DRM_IOCTL_RADEON_CLEAR () { &DRM_IOW(  &DRM_COMMAND_BASE +  &DRM_RADEON_CLEAR,  &drm_radeon_clear_t);}' unless defined(&DRM_IOCTL_RADEON_CLEAR);
    eval 'sub DRM_IOCTL_RADEON_VERTEX () { &DRM_IOW(  &DRM_COMMAND_BASE +  &DRM_RADEON_VERTEX,  &drm_radeon_vertex_t);}' unless defined(&DRM_IOCTL_RADEON_VERTEX);
    eval 'sub DRM_IOCTL_RADEON_INDICES () { &DRM_IOW(  &DRM_COMMAND_BASE +  &DRM_RADEON_INDICES,  &drm_radeon_indices_t);}' unless defined(&DRM_IOCTL_RADEON_INDICES);
    eval 'sub DRM_IOCTL_RADEON_STIPPLE () { &DRM_IOW(  &DRM_COMMAND_BASE +  &DRM_RADEON_STIPPLE,  &drm_radeon_stipple_t);}' unless defined(&DRM_IOCTL_RADEON_STIPPLE);
    eval 'sub DRM_IOCTL_RADEON_INDIRECT () { &DRM_IOWR( &DRM_COMMAND_BASE +  &DRM_RADEON_INDIRECT,  &drm_radeon_indirect_t);}' unless defined(&DRM_IOCTL_RADEON_INDIRECT);
    eval 'sub DRM_IOCTL_RADEON_TEXTURE () { &DRM_IOWR( &DRM_COMMAND_BASE +  &DRM_RADEON_TEXTURE,  &drm_radeon_texture_t);}' unless defined(&DRM_IOCTL_RADEON_TEXTURE);
    eval 'sub DRM_IOCTL_RADEON_VERTEX2 () { &DRM_IOW(  &DRM_COMMAND_BASE +  &DRM_RADEON_VERTEX2,  &drm_radeon_vertex2_t);}' unless defined(&DRM_IOCTL_RADEON_VERTEX2);
    eval 'sub DRM_IOCTL_RADEON_CMDBUF () { &DRM_IOW(  &DRM_COMMAND_BASE +  &DRM_RADEON_CMDBUF,  &drm_radeon_cmd_buffer_t);}' unless defined(&DRM_IOCTL_RADEON_CMDBUF);
    eval 'sub DRM_IOCTL_RADEON_GETPARAM () { &DRM_IOWR( &DRM_COMMAND_BASE +  &DRM_RADEON_GETPARAM,  &drm_radeon_getparam_t);}' unless defined(&DRM_IOCTL_RADEON_GETPARAM);
    eval 'sub DRM_IOCTL_RADEON_FLIP () { &DRM_IO(  &DRM_COMMAND_BASE +  &DRM_RADEON_FLIP);}' unless defined(&DRM_IOCTL_RADEON_FLIP);
    eval 'sub DRM_IOCTL_RADEON_ALLOC () { &DRM_IOWR( &DRM_COMMAND_BASE +  &DRM_RADEON_ALLOC,  &drm_radeon_mem_alloc_t);}' unless defined(&DRM_IOCTL_RADEON_ALLOC);
    eval 'sub DRM_IOCTL_RADEON_FREE () { &DRM_IOW(  &DRM_COMMAND_BASE +  &DRM_RADEON_FREE,  &drm_radeon_mem_free_t);}' unless defined(&DRM_IOCTL_RADEON_FREE);
    eval 'sub DRM_IOCTL_RADEON_INIT_HEAP () { &DRM_IOW(  &DRM_COMMAND_BASE +  &DRM_RADEON_INIT_HEAP,  &drm_radeon_mem_init_heap_t);}' unless defined(&DRM_IOCTL_RADEON_INIT_HEAP);
    eval 'sub DRM_IOCTL_RADEON_IRQ_EMIT () { &DRM_IOWR( &DRM_COMMAND_BASE +  &DRM_RADEON_IRQ_EMIT,  &drm_radeon_irq_emit_t);}' unless defined(&DRM_IOCTL_RADEON_IRQ_EMIT);
    eval 'sub DRM_IOCTL_RADEON_IRQ_WAIT () { &DRM_IOW(  &DRM_COMMAND_BASE +  &DRM_RADEON_IRQ_WAIT,  &drm_radeon_irq_wait_t);}' unless defined(&DRM_IOCTL_RADEON_IRQ_WAIT);
    eval 'sub DRM_IOCTL_RADEON_CP_RESUME () { &DRM_IO(  &DRM_COMMAND_BASE +  &DRM_RADEON_CP_RESUME);}' unless defined(&DRM_IOCTL_RADEON_CP_RESUME);
    eval 'sub DRM_IOCTL_RADEON_SETPARAM () { &DRM_IOW(  &DRM_COMMAND_BASE +  &DRM_RADEON_SETPARAM,  &drm_radeon_setparam_t);}' unless defined(&DRM_IOCTL_RADEON_SETPARAM);
    eval 'sub DRM_IOCTL_RADEON_SURF_ALLOC () { &DRM_IOW(  &DRM_COMMAND_BASE +  &DRM_RADEON_SURF_ALLOC,  &drm_radeon_surface_alloc_t);}' unless defined(&DRM_IOCTL_RADEON_SURF_ALLOC);
    eval 'sub DRM_IOCTL_RADEON_SURF_FREE () { &DRM_IOW(  &DRM_COMMAND_BASE +  &DRM_RADEON_SURF_FREE,  &drm_radeon_surface_free_t);}' unless defined(&DRM_IOCTL_RADEON_SURF_FREE);
    eval("sub RADEON_INIT_CP () { 0x01; }") unless defined(&RADEON_INIT_CP);
    eval("sub RADEON_CLEANUP_CP () { 0x02; }") unless defined(&RADEON_CLEANUP_CP);
    eval("sub RADEON_INIT_R200_CP () { 0x03; }") unless defined(&RADEON_INIT_R200_CP);
    eval("sub RADEON_INIT_R300_CP () { 0x04; }") unless defined(&RADEON_INIT_R300_CP);
    eval("sub RADEON_INIT_FULLSCREEN () { 0x01; }") unless defined(&RADEON_INIT_FULLSCREEN);
    eval("sub RADEON_CLEANUP_FULLSCREEN () { 0x02; }") unless defined(&RADEON_CLEANUP_FULLSCREEN);
    eval 'sub CLEAR_X1 () {0;}' unless defined(&CLEAR_X1);
    eval 'sub CLEAR_Y1 () {1;}' unless defined(&CLEAR_Y1);
    eval 'sub CLEAR_X2 () {2;}' unless defined(&CLEAR_X2);
    eval 'sub CLEAR_Y2 () {3;}' unless defined(&CLEAR_Y2);
    eval 'sub CLEAR_DEPTH () {4;}' unless defined(&CLEAR_DEPTH);
    eval 'sub RADEON_CARD_PCI () {0;}' unless defined(&RADEON_CARD_PCI);
    eval 'sub RADEON_CARD_AGP () {1;}' unless defined(&RADEON_CARD_AGP);
    eval 'sub RADEON_CARD_PCIE () {2;}' unless defined(&RADEON_CARD_PCIE);
    eval 'sub RADEON_PARAM_GART_BUFFER_OFFSET () {1;}' unless defined(&RADEON_PARAM_GART_BUFFER_OFFSET);
    eval 'sub RADEON_PARAM_LAST_FRAME () {2;}' unless defined(&RADEON_PARAM_LAST_FRAME);
    eval 'sub RADEON_PARAM_LAST_DISPATCH () {3;}' unless defined(&RADEON_PARAM_LAST_DISPATCH);
    eval 'sub RADEON_PARAM_LAST_CLEAR () {4;}' unless defined(&RADEON_PARAM_LAST_CLEAR);
    eval 'sub RADEON_PARAM_IRQ_NR () {5;}' unless defined(&RADEON_PARAM_IRQ_NR);
    eval 'sub RADEON_PARAM_GART_BASE () {6;}' unless defined(&RADEON_PARAM_GART_BASE);
    eval 'sub RADEON_PARAM_REGISTER_HANDLE () {7;}' unless defined(&RADEON_PARAM_REGISTER_HANDLE);
    eval 'sub RADEON_PARAM_STATUS_HANDLE () {8;}' unless defined(&RADEON_PARAM_STATUS_HANDLE);
    eval 'sub RADEON_PARAM_SAREA_HANDLE () {9;}' unless defined(&RADEON_PARAM_SAREA_HANDLE);
    eval 'sub RADEON_PARAM_GART_TEX_HANDLE () {10;}' unless defined(&RADEON_PARAM_GART_TEX_HANDLE);
    eval 'sub RADEON_PARAM_SCRATCH_OFFSET () {11;}' unless defined(&RADEON_PARAM_SCRATCH_OFFSET);
    eval 'sub RADEON_PARAM_CARD_TYPE () {12;}' unless defined(&RADEON_PARAM_CARD_TYPE);
    eval 'sub RADEON_PARAM_VBLANK_CRTC () {13;}' unless defined(&RADEON_PARAM_VBLANK_CRTC);
    eval 'sub RADEON_PARAM_FB_LOCATION () {14;}' unless defined(&RADEON_PARAM_FB_LOCATION);
    eval 'sub RADEON_PARAM_NUM_GB_PIPES () {15;}' unless defined(&RADEON_PARAM_NUM_GB_PIPES);
    eval 'sub RADEON_MEM_REGION_GART () {1;}' unless defined(&RADEON_MEM_REGION_GART);
    eval 'sub RADEON_MEM_REGION_FB () {2;}' unless defined(&RADEON_MEM_REGION_FB);
    eval 'sub RADEON_SETPARAM_FB_LOCATION () {1;}' unless defined(&RADEON_SETPARAM_FB_LOCATION);
    eval 'sub RADEON_SETPARAM_SWITCH_TILING () {2;}' unless defined(&RADEON_SETPARAM_SWITCH_TILING);
    eval 'sub RADEON_SETPARAM_PCIGART_LOCATION () {3;}' unless defined(&RADEON_SETPARAM_PCIGART_LOCATION);
    eval 'sub RADEON_SETPARAM_NEW_MEMMAP () {4;}' unless defined(&RADEON_SETPARAM_NEW_MEMMAP);
    eval 'sub RADEON_SETPARAM_PCIGART_TABLE_SIZE () {5;}' unless defined(&RADEON_SETPARAM_PCIGART_TABLE_SIZE);
    eval 'sub RADEON_SETPARAM_VBLANK_CRTC () {6;}' unless defined(&RADEON_SETPARAM_VBLANK_CRTC);
    eval 'sub DRM_RADEON_VBLANK_CRTC1 () {1;}' unless defined(&DRM_RADEON_VBLANK_CRTC1);
    eval 'sub DRM_RADEON_VBLANK_CRTC2 () {2;}' unless defined(&DRM_RADEON_VBLANK_CRTC2);
}
1;
