require '_h2ph_pre.ph';

no warnings 'redefine';

unless(defined(&_I915_DRV_H_)) {
    eval 'sub _I915_DRV_H_ () {1;}' unless defined(&_I915_DRV_H_);
    eval 'sub DRIVER_AUTHOR () {"Tungsten Graphics, Inc.";}' unless defined(&DRIVER_AUTHOR);
    eval 'sub DRIVER_NAME () {"i915";}' unless defined(&DRIVER_NAME);
    eval 'sub DRIVER_DESC () {"Intel Graphics";}' unless defined(&DRIVER_DESC);
    eval 'sub DRIVER_DATE () {"20080312";}' unless defined(&DRIVER_DATE);
    if(defined( &__linux__)) {
	eval 'sub I915_HAVE_FENCE () {1;}' unless defined(&I915_HAVE_FENCE);
	eval 'sub I915_HAVE_BUFFER () {1;}' unless defined(&I915_HAVE_BUFFER);
    }
    eval 'sub DRIVER_MAJOR () {1;}' unless defined(&DRIVER_MAJOR);
    if(defined( &I915_HAVE_FENCE)  && defined( &I915_HAVE_BUFFER)) {
	eval 'sub DRIVER_MINOR () {13;}' unless defined(&DRIVER_MINOR);
    } else {
	eval 'sub DRIVER_MINOR () {6;}' unless defined(&DRIVER_MINOR);
    }
    eval 'sub DRIVER_PATCHLEVEL () {0;}' unless defined(&DRIVER_PATCHLEVEL);
    eval("sub PIPE_A () { 0; }") unless defined(&PIPE_A);
    eval("sub PIPE_B () { 1; }") unless defined(&PIPE_B);
    if(defined(&I915_HAVE_BUFFER)) {
	eval 'sub I915_MAX_VALIDATE_BUFFERS () {4096;}' unless defined(&I915_MAX_VALIDATE_BUFFERS);
    }
    if(defined(&__linux__)) {
    }
    if(defined(&I915_HAVE_FENCE)) {
    }
    if(defined(&I915_HAVE_BUFFER)) {
    }
    if(defined( &I915_HAVE_BUFFER)) {
    }
    if(defined(&__linux__)) {
    }
    eval("sub CHIP_I8XX () { 0x01; }") unless defined(&CHIP_I8XX);
    eval("sub CHIP_I9XX () { 0x02; }") unless defined(&CHIP_I9XX);
    eval("sub CHIP_I915 () { 0x04; }") unless defined(&CHIP_I915);
    eval("sub CHIP_I965 () { 0x08; }") unless defined(&CHIP_I965);
    if(defined(&I915_HAVE_FENCE)) {
    }
    if(defined(&I915_HAVE_BUFFER)) {
    }
    if(defined(&__linux__)) {
    }
    if(defined(&__linux__)) {
	if((defined(&LINUX_VERSION_CODE) ? &LINUX_VERSION_CODE : 0) <  &KERNEL_VERSION(2,6,25)) {
	}
    }
    eval 'sub I915_READ {
        my($reg) = @_;
	    eval q( &DRM_READ32( ($dev_priv->{mmio_map}), ($reg)));
    }' unless defined(&I915_READ);
    eval 'sub I915_WRITE {
        my($reg,$val) = @_;
	    eval q( &DRM_WRITE32( ($dev_priv->{mmio_map}), ($reg), ($val)));
    }' unless defined(&I915_WRITE);
    eval 'sub I915_READ16 {
        my($reg) = @_;
	    eval q( &DRM_READ16( ($dev_priv->{mmio_map}), ($reg)));
    }' unless defined(&I915_READ16);
    eval 'sub I915_WRITE16 {
        my($reg,$val) = @_;
	    eval q( &DRM_WRITE16( ($dev_priv->{mmio_map}), ($reg), ($val)));
    }' unless defined(&I915_WRITE16);
    eval 'sub I915_READ8 {
        my($reg) = @_;
	    eval q( &DRM_READ8( ($dev_priv->{mmio_map}), ($reg)));
    }' unless defined(&I915_READ8);
    eval 'sub I915_WRITE8 {
        my($reg,$val) = @_;
	    eval q( &DRM_WRITE8( ($dev_priv->{mmio_map}), ($reg), ($val)));
    }' unless defined(&I915_WRITE8);
    if(defined( &__FreeBSD__)) {
    }
    eval 'sub I915_VERBOSE () {0;}' unless defined(&I915_VERBOSE);
    eval 'sub PRIMARY_RINGBUFFER_SIZE () {(128*1024);}' unless defined(&PRIMARY_RINGBUFFER_SIZE);
    eval 'sub RING_LOCALS () {\'unsigned int outring\',  &ringmask,  &outcount;  &volatile \'char\' * &virt;;}' unless defined(&RING_LOCALS);
    eval 'sub BEGIN_LP_RING {
        my($n) = @_;
	    eval q( &do {  &if ( &I915_VERBOSE)  &DRM_DEBUG(\\"BEGIN_LP_RING(%d)\\\\n\\", ($n));  &if ( ($dev_priv->{ring}->{space}) < ($n)*4)  &i915_wait_ring( &dev, ($n)*4,  &__FUNCTION__);  &outcount = 0;  &outring =  ($dev_priv->{ring}->{tail});  &ringmask =  ($dev_priv->{ring}->{tail_mask});  &virt =  ($dev_priv->{ring}->{virtual_start}); }  &while (0));
    }' unless defined(&BEGIN_LP_RING);
    eval 'sub OUT_RING {
        my($n) = @_;
	    eval q( &do {  &if ( &I915_VERBOSE)  &DRM_DEBUG(\\"   OUT_RING %x\\\\n\\", ($n)); *( &volatile \'unsigned int\' *)( &virt +  &outring) = ($n);  &outcount++;  &outring += 4;  &outring &=  &ringmask; }  &while (0));
    }' unless defined(&OUT_RING);
    eval 'sub ADVANCE_LP_RING () {
        eval q( &do {  &if ( &I915_VERBOSE)  &DRM_DEBUG(\\"ADVANCE_LP_RING %x\\\\n\\",  &outring);  ($dev_priv->{ring}->{tail}) =  &outring;  ($dev_priv->{ring}->{space}) -=  &outcount * 4;  &I915_WRITE( &PRB0_TAIL,  &outring); }  &while(0));
    }' unless defined(&ADVANCE_LP_RING);
    eval 'sub INTEL_GMCH_CTRL () {0x52;}' unless defined(&INTEL_GMCH_CTRL);
    eval 'sub INTEL_GMCH_ENABLED () {0x4;}' unless defined(&INTEL_GMCH_ENABLED);
    eval 'sub INTEL_GMCH_MEM_MASK () {0x1;}' unless defined(&INTEL_GMCH_MEM_MASK);
    eval 'sub INTEL_GMCH_MEM_64M () {0x1;}' unless defined(&INTEL_GMCH_MEM_64M);
    eval 'sub INTEL_GMCH_MEM_128M () {0;}' unless defined(&INTEL_GMCH_MEM_128M);
    eval 'sub INTEL_855_GMCH_GMS_MASK () {(0x7 << 4);}' unless defined(&INTEL_855_GMCH_GMS_MASK);
    eval 'sub INTEL_855_GMCH_GMS_DISABLED () {(0x << 4);}' unless defined(&INTEL_855_GMCH_GMS_DISABLED);
    eval 'sub INTEL_855_GMCH_GMS_STOLEN_1M () {(0x1 << 4);}' unless defined(&INTEL_855_GMCH_GMS_STOLEN_1M);
    eval 'sub INTEL_855_GMCH_GMS_STOLEN_4M () {(0x2 << 4);}' unless defined(&INTEL_855_GMCH_GMS_STOLEN_4M);
    eval 'sub INTEL_855_GMCH_GMS_STOLEN_8M () {(0x3 << 4);}' unless defined(&INTEL_855_GMCH_GMS_STOLEN_8M);
    eval 'sub INTEL_855_GMCH_GMS_STOLEN_16M () {(0x4 << 4);}' unless defined(&INTEL_855_GMCH_GMS_STOLEN_16M);
    eval 'sub INTEL_855_GMCH_GMS_STOLEN_32M () {(0x5 << 4);}' unless defined(&INTEL_855_GMCH_GMS_STOLEN_32M);
    eval 'sub INTEL_915G_GMCH_GMS_STOLEN_48M () {(0x6 << 4);}' unless defined(&INTEL_915G_GMCH_GMS_STOLEN_48M);
    eval 'sub INTEL_915G_GMCH_GMS_STOLEN_64M () {(0x7 << 4);}' unless defined(&INTEL_915G_GMCH_GMS_STOLEN_64M);
    eval 'sub HPLLCC () {0xc0;}' unless defined(&HPLLCC);
    eval 'sub GC_CLOCK_CONTROL_MASK () {(3<< 0);}' unless defined(&GC_CLOCK_CONTROL_MASK);
    eval 'sub GC_CLOCK_133_200 () {(0<< 0);}' unless defined(&GC_CLOCK_133_200);
    eval 'sub GC_CLOCK_100_200 () {(1<< 0);}' unless defined(&GC_CLOCK_100_200);
    eval 'sub GC_CLOCK_100_133 () {(2<< 0);}' unless defined(&GC_CLOCK_100_133);
    eval 'sub GC_CLOCK_166_250 () {(3<< 0);}' unless defined(&GC_CLOCK_166_250);
    eval 'sub GCFGC () {0xf0;}' unless defined(&GCFGC);
    eval 'sub GC_LOW_FREQUENCY_ENABLE () {(1<< 7);}' unless defined(&GC_LOW_FREQUENCY_ENABLE);
    eval 'sub GC_DISPLAY_CLOCK_190_200_MHZ () {(0<< 4);}' unless defined(&GC_DISPLAY_CLOCK_190_200_MHZ);
    eval 'sub GC_DISPLAY_CLOCK_333_MHZ () {(4<< 4);}' unless defined(&GC_DISPLAY_CLOCK_333_MHZ);
    eval 'sub GC_DISPLAY_CLOCK_MASK () {(7<< 4);}' unless defined(&GC_DISPLAY_CLOCK_MASK);
    eval 'sub LBB () {0xf4;}' unless defined(&LBB);
    eval 'sub VGA_ST01_MDA () {0x3ba;}' unless defined(&VGA_ST01_MDA);
    eval 'sub VGA_ST01_CGA () {0x3da;}' unless defined(&VGA_ST01_CGA);
    eval 'sub VGA_MSR_WRITE () {0x3c2;}' unless defined(&VGA_MSR_WRITE);
    eval 'sub VGA_MSR_READ () {0x3cc;}' unless defined(&VGA_MSR_READ);
    eval 'sub VGA_MSR_MEM_EN () {(1<<1);}' unless defined(&VGA_MSR_MEM_EN);
    eval 'sub VGA_MSR_CGA_MODE () {(1<<0);}' unless defined(&VGA_MSR_CGA_MODE);
    eval 'sub VGA_SR_INDEX () {0x3c4;}' unless defined(&VGA_SR_INDEX);
    eval 'sub VGA_SR_DATA () {0x3c5;}' unless defined(&VGA_SR_DATA);
    eval 'sub VGA_AR_INDEX () {0x3c0;}' unless defined(&VGA_AR_INDEX);
    eval 'sub VGA_AR_VID_EN () {(1<<5);}' unless defined(&VGA_AR_VID_EN);
    eval 'sub VGA_AR_DATA_WRITE () {0x3c0;}' unless defined(&VGA_AR_DATA_WRITE);
    eval 'sub VGA_AR_DATA_READ () {0x3c1;}' unless defined(&VGA_AR_DATA_READ);
    eval 'sub VGA_GR_INDEX () {0x3ce;}' unless defined(&VGA_GR_INDEX);
    eval 'sub VGA_GR_DATA () {0x3cf;}' unless defined(&VGA_GR_DATA);
    eval 'sub VGA_GR_MEM_READ_MODE_SHIFT () {3;}' unless defined(&VGA_GR_MEM_READ_MODE_SHIFT);
    eval 'sub VGA_GR_MEM_READ_MODE_PLANE () {1;}' unless defined(&VGA_GR_MEM_READ_MODE_PLANE);
    eval 'sub VGA_GR_MEM_MODE_MASK () {0xc;}' unless defined(&VGA_GR_MEM_MODE_MASK);
    eval 'sub VGA_GR_MEM_MODE_SHIFT () {2;}' unless defined(&VGA_GR_MEM_MODE_SHIFT);
    eval 'sub VGA_GR_MEM_A0000_AFFFF () {0;}' unless defined(&VGA_GR_MEM_A0000_AFFFF);
    eval 'sub VGA_GR_MEM_A0000_BFFFF () {1;}' unless defined(&VGA_GR_MEM_A0000_BFFFF);
    eval 'sub VGA_GR_MEM_B0000_B7FFF () {2;}' unless defined(&VGA_GR_MEM_B0000_B7FFF);
    eval 'sub VGA_GR_MEM_B0000_BFFFF () {3;}' unless defined(&VGA_GR_MEM_B0000_BFFFF);
    eval 'sub VGA_DACMASK () {0x3c6;}' unless defined(&VGA_DACMASK);
    eval 'sub VGA_DACRX () {0x3c7;}' unless defined(&VGA_DACRX);
    eval 'sub VGA_DACWX () {0x3c8;}' unless defined(&VGA_DACWX);
    eval 'sub VGA_DACDATA () {0x3c9;}' unless defined(&VGA_DACDATA);
    eval 'sub VGA_CR_INDEX_MDA () {0x3b4;}' unless defined(&VGA_CR_INDEX_MDA);
    eval 'sub VGA_CR_DATA_MDA () {0x3b5;}' unless defined(&VGA_CR_DATA_MDA);
    eval 'sub VGA_CR_INDEX_CGA () {0x3d4;}' unless defined(&VGA_CR_INDEX_CGA);
    eval 'sub VGA_CR_DATA_CGA () {0x3d5;}' unless defined(&VGA_CR_DATA_CGA);
    eval 'sub MI_INSTR {
        my($opcode, $flags) = @_;
	    eval q(((($opcode) << 23) | ($flags)));
    }' unless defined(&MI_INSTR);
    eval 'sub MI_NOOP () { &MI_INSTR(0, 0);}' unless defined(&MI_NOOP);
    eval 'sub MI_USER_INTERRUPT () { &MI_INSTR(0x2, 0);}' unless defined(&MI_USER_INTERRUPT);
    eval 'sub MI_WAIT_FOR_EVENT () { &MI_INSTR(0x3, 0);}' unless defined(&MI_WAIT_FOR_EVENT);
    eval 'sub MI_WAIT_FOR_PLANE_B_FLIP () {(1<<6);}' unless defined(&MI_WAIT_FOR_PLANE_B_FLIP);
    eval 'sub MI_WAIT_FOR_PLANE_A_FLIP () {(1<<2);}' unless defined(&MI_WAIT_FOR_PLANE_A_FLIP);
    eval 'sub MI_WAIT_FOR_PLANE_A_SCANLINES () {(1<<1);}' unless defined(&MI_WAIT_FOR_PLANE_A_SCANLINES);
    eval 'sub MI_FLUSH () { &MI_INSTR(0x4, 0);}' unless defined(&MI_FLUSH);
    eval 'sub MI_READ_FLUSH () {(1<< 0);}' unless defined(&MI_READ_FLUSH);
    eval 'sub MI_EXE_FLUSH () {(1<< 1);}' unless defined(&MI_EXE_FLUSH);
    eval 'sub MI_NO_WRITE_FLUSH () {(1<< 2);}' unless defined(&MI_NO_WRITE_FLUSH);
    eval 'sub MI_SCENE_COUNT () {(1<< 3);}' unless defined(&MI_SCENE_COUNT);
    eval 'sub MI_END_SCENE () {(1<< 4);}' unless defined(&MI_END_SCENE);
    eval 'sub MI_BATCH_BUFFER_END () { &MI_INSTR(0xa, 0);}' unless defined(&MI_BATCH_BUFFER_END);
    eval 'sub MI_REPORT_HEAD () { &MI_INSTR(0x7, 0);}' unless defined(&MI_REPORT_HEAD);
    eval 'sub MI_LOAD_SCAN_LINES_INCL () { &MI_INSTR(0x12, 0);}' unless defined(&MI_LOAD_SCAN_LINES_INCL);
    eval 'sub MI_STORE_DWORD_IMM () { &MI_INSTR(0x20, 1);}' unless defined(&MI_STORE_DWORD_IMM);
    eval 'sub MI_MEM_VIRTUAL () {(1<< 22);}' unless defined(&MI_MEM_VIRTUAL);
    eval 'sub MI_STORE_DWORD_INDEX () { &MI_INSTR(0x21, 1);}' unless defined(&MI_STORE_DWORD_INDEX);
    eval 'sub MI_LOAD_REGISTER_IMM () { &MI_INSTR(0x22, 1);}' unless defined(&MI_LOAD_REGISTER_IMM);
    eval 'sub MI_BATCH_BUFFER () { &MI_INSTR(0x30, 1);}' unless defined(&MI_BATCH_BUFFER);
    eval 'sub MI_BATCH_NON_SECURE () {(1);}' unless defined(&MI_BATCH_NON_SECURE);
    eval 'sub MI_BATCH_NON_SECURE_I965 () {(1<<8);}' unless defined(&MI_BATCH_NON_SECURE_I965);
    eval 'sub MI_BATCH_BUFFER_START () { &MI_INSTR(0x31, 0);}' unless defined(&MI_BATCH_BUFFER_START);
    eval 'sub BREADCRUMB_BITS () {31;}' unless defined(&BREADCRUMB_BITS);
    eval 'sub BREADCRUMB_MASK () {((1 <<  &BREADCRUMB_BITS) - 1);}' unless defined(&BREADCRUMB_MASK);
    eval 'sub READ_BREADCRUMB {
        my($dev_priv) = @_;
	    eval q(((( &volatile  &u32*)( ($dev_priv->{hw_status_page})))[5]));
    }' unless defined(&READ_BREADCRUMB);
    eval 'sub READ_HWSP {
        my($dev_priv, $reg) = @_;
	    eval q(((( &volatile  &u32*)( ($dev_priv->{hw_status_page})))[$reg]));
    }' unless defined(&READ_HWSP);
    eval 'sub I915_GEM_HWS_INDEX () {0x10;}' unless defined(&I915_GEM_HWS_INDEX);
    eval 'sub GFX_INSTR {
        my($opcode, $flags) = @_;
	    eval q(((0x3 << 29) | (($opcode) << 24) | ($flags)));
    }' unless defined(&GFX_INSTR);
    eval 'sub GFX_OP_RASTER_RULES () {((0x3<<29)|(0x7<<24));}' unless defined(&GFX_OP_RASTER_RULES);
    eval 'sub GFX_OP_SCISSOR () {((0x3<<29)|(0x1c<<24)|(0x10<<19));}' unless defined(&GFX_OP_SCISSOR);
    eval 'sub SC_UPDATE_SCISSOR () {(0x1<<1);}' unless defined(&SC_UPDATE_SCISSOR);
    eval 'sub SC_ENABLE_MASK () {(0x1<<0);}' unless defined(&SC_ENABLE_MASK);
    eval 'sub SC_ENABLE () {(0x1<<0);}' unless defined(&SC_ENABLE);
    eval 'sub GFX_OP_LOAD_INDIRECT () {((0x3<<29)|(0x1d<<24)|(0x7<<16));}' unless defined(&GFX_OP_LOAD_INDIRECT);
    eval 'sub GFX_OP_SCISSOR_INFO () {((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1));}' unless defined(&GFX_OP_SCISSOR_INFO);
    eval 'sub SCI_YMIN_MASK () {(0xffff<<16);}' unless defined(&SCI_YMIN_MASK);
    eval 'sub SCI_XMIN_MASK () {(0xffff<<0);}' unless defined(&SCI_XMIN_MASK);
    eval 'sub SCI_YMAX_MASK () {(0xffff<<16);}' unless defined(&SCI_YMAX_MASK);
    eval 'sub SCI_XMAX_MASK () {(0xffff<<0);}' unless defined(&SCI_XMAX_MASK);
    eval 'sub GFX_OP_SCISSOR_ENABLE () {((0x3<<29)|(0x1c<<24)|(0x10<<19));}' unless defined(&GFX_OP_SCISSOR_ENABLE);
    eval 'sub GFX_OP_SCISSOR_RECT () {((0x3<<29)|(0x1d<<24)|(0x81<<16)|1);}' unless defined(&GFX_OP_SCISSOR_RECT);
    eval 'sub GFX_OP_COLOR_FACTOR () {((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x);}' unless defined(&GFX_OP_COLOR_FACTOR);
    eval 'sub GFX_OP_STIPPLE () {((0x3<<29)|(0x1d<<24)|(0x83<<16));}' unless defined(&GFX_OP_STIPPLE);
    eval 'sub GFX_OP_MAP_INFO () {((0x3<<29)|(0x1d<<24)|0x4);}' unless defined(&GFX_OP_MAP_INFO);
    eval 'sub GFX_OP_DESTBUFFER_VARS () {((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x);}' unless defined(&GFX_OP_DESTBUFFER_VARS);
    eval 'sub GFX_OP_DRAWRECT_INFO () {((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3));}' unless defined(&GFX_OP_DRAWRECT_INFO);
    eval 'sub GFX_OP_DRAWRECT_INFO_I965 () {((0x7900<<16)|0x2);}' unless defined(&GFX_OP_DRAWRECT_INFO_I965);
    eval 'sub SRC_COPY_BLT_CMD () {((2<<29)|(0x43<<22)|4);}' unless defined(&SRC_COPY_BLT_CMD);
    eval 'sub XY_SRC_COPY_BLT_CMD () {((2<<29)|(0x53<<22)|6);}' unless defined(&XY_SRC_COPY_BLT_CMD);
    eval 'sub XY_MONO_SRC_COPY_IMM_BLT () {((2<<29)|(0x71<<22)|5);}' unless defined(&XY_MONO_SRC_COPY_IMM_BLT);
    eval 'sub XY_SRC_COPY_BLT_WRITE_ALPHA () {(1<<21);}' unless defined(&XY_SRC_COPY_BLT_WRITE_ALPHA);
    eval 'sub XY_SRC_COPY_BLT_WRITE_RGB () {(1<<20);}' unless defined(&XY_SRC_COPY_BLT_WRITE_RGB);
    eval 'sub BLT_DEPTH_8 () {(0<<24);}' unless defined(&BLT_DEPTH_8);
    eval 'sub BLT_DEPTH_16_565 () {(1<<24);}' unless defined(&BLT_DEPTH_16_565);
    eval 'sub BLT_DEPTH_16_1555 () {(2<<24);}' unless defined(&BLT_DEPTH_16_1555);
    eval 'sub BLT_DEPTH_32 () {(3<<24);}' unless defined(&BLT_DEPTH_32);
    eval 'sub BLT_ROP_GXCOPY () {(0xcc<<16);}' unless defined(&BLT_ROP_GXCOPY);
    eval 'sub XY_SRC_COPY_BLT_SRC_TILED () {(1<<15);}' unless defined(&XY_SRC_COPY_BLT_SRC_TILED);
    eval 'sub XY_SRC_COPY_BLT_DST_TILED () {(1<<11);}' unless defined(&XY_SRC_COPY_BLT_DST_TILED);
    eval 'sub CMD_OP_DISPLAYBUFFER_INFO () {((0x<<29)|(0x14<<23)|2);}' unless defined(&CMD_OP_DISPLAYBUFFER_INFO);
    eval 'sub ASYNC_FLIP () {(1<<22);}' unless defined(&ASYNC_FLIP);
    eval 'sub DISPLAY_PLANE_A () {(0<<20);}' unless defined(&DISPLAY_PLANE_A);
    eval 'sub DISPLAY_PLANE_B () {(1<<20);}' unless defined(&DISPLAY_PLANE_B);
    eval 'sub PRB0_TAIL () {0x2030;}' unless defined(&PRB0_TAIL);
    eval 'sub PRB0_HEAD () {0x2034;}' unless defined(&PRB0_HEAD);
    eval 'sub PRB0_START () {0x2038;}' unless defined(&PRB0_START);
    eval 'sub PRB0_CTL () {0x203c;}' unless defined(&PRB0_CTL);
    eval 'sub TAIL_ADDR () {0x1ffff8;}' unless defined(&TAIL_ADDR);
    eval 'sub HEAD_WRAP_COUNT () {0xffe00000;}' unless defined(&HEAD_WRAP_COUNT);
    eval 'sub HEAD_WRAP_ONE () {0x200000;}' unless defined(&HEAD_WRAP_ONE);
    eval 'sub HEAD_ADDR () {0x1ffffc;}' unless defined(&HEAD_ADDR);
    eval 'sub RING_NR_PAGES () {0x1ff000;}' unless defined(&RING_NR_PAGES);
    eval 'sub RING_REPORT_MASK () {0x6;}' unless defined(&RING_REPORT_MASK);
    eval 'sub RING_REPORT_64K () {0x2;}' unless defined(&RING_REPORT_64K);
    eval 'sub RING_REPORT_128K () {0x4;}' unless defined(&RING_REPORT_128K);
    eval 'sub RING_NO_REPORT () {0x;}' unless defined(&RING_NO_REPORT);
    eval 'sub RING_VALID_MASK () {0x1;}' unless defined(&RING_VALID_MASK);
    eval 'sub RING_VALID () {0x1;}' unless defined(&RING_VALID);
    eval 'sub RING_INVALID () {0x;}' unless defined(&RING_INVALID);
    eval 'sub PRB1_TAIL () {0x2040;}' unless defined(&PRB1_TAIL);
    eval 'sub PRB1_HEAD () {0x2044;}' unless defined(&PRB1_HEAD);
    eval 'sub PRB1_START () {0x2048;}' unless defined(&PRB1_START);
    eval 'sub PRB1_CTL () {0x204c;}' unless defined(&PRB1_CTL);
    eval 'sub HWS_PGA () {0x2080;}' unless defined(&HWS_PGA);
    eval 'sub IPEIR () {0x2088;}' unless defined(&IPEIR);
    eval 'sub NOPID () {0x2094;}' unless defined(&NOPID);
    eval 'sub HWSTAM () {0x2098;}' unless defined(&HWSTAM);
    eval 'sub SCPD0 () {0x209c;}' unless defined(&SCPD0);
    eval 'sub IER () {0x20a0;}' unless defined(&IER);
    eval 'sub IIR () {0x20a4;}' unless defined(&IIR);
    eval 'sub IMR () {0x20a8;}' unless defined(&IMR);
    eval 'sub ISR () {0x20ac;}' unless defined(&ISR);
    eval 'sub I915_PIPE_CONTROL_NOTIFY_INTERRUPT () {(1<<18);}' unless defined(&I915_PIPE_CONTROL_NOTIFY_INTERRUPT);
    eval 'sub I915_DISPLAY_PORT_INTERRUPT () {(1<<17);}' unless defined(&I915_DISPLAY_PORT_INTERRUPT);
    eval 'sub I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT () {(1<<15);}' unless defined(&I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
    eval 'sub I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT () {(1<<14);}' unless defined(&I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT);
    eval 'sub I915_HWB_OOM_INTERRUPT () {(1<<13);}' unless defined(&I915_HWB_OOM_INTERRUPT);
    eval 'sub I915_SYNC_STATUS_INTERRUPT () {(1<<12);}' unless defined(&I915_SYNC_STATUS_INTERRUPT);
    eval 'sub I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT () {(1<<11);}' unless defined(&I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT);
    eval 'sub I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT () {(1<<10);}' unless defined(&I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
    eval 'sub I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT () {(1<<9);}' unless defined(&I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT);
    eval 'sub I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT () {(1<<8);}' unless defined(&I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT);
    eval 'sub I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT () {(1<<7);}' unless defined(&I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT);
    eval 'sub I915_DISPLAY_PIPE_A_EVENT_INTERRUPT () {(1<<6);}' unless defined(&I915_DISPLAY_PIPE_A_EVENT_INTERRUPT);
    eval 'sub I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT () {(1<<5);}' unless defined(&I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT);
    eval 'sub I915_DISPLAY_PIPE_B_EVENT_INTERRUPT () {(1<<4);}' unless defined(&I915_DISPLAY_PIPE_B_EVENT_INTERRUPT);
    eval 'sub I915_DEBUG_INTERRUPT () {(1<<2);}' unless defined(&I915_DEBUG_INTERRUPT);
    eval 'sub I915_USER_INTERRUPT () {(1<<1);}' unless defined(&I915_USER_INTERRUPT);
    eval 'sub I915_ASLE_INTERRUPT () {(1<<0);}' unless defined(&I915_ASLE_INTERRUPT);
    eval 'sub EIR () {0x20b0;}' unless defined(&EIR);
    eval 'sub EMR () {0x20b4;}' unless defined(&EMR);
    eval 'sub ESR () {0x20b8;}' unless defined(&ESR);
    eval 'sub INSTPM () {0x20c0;}' unless defined(&INSTPM);
    eval 'sub FW_BLC () {0x20d8;}' unless defined(&FW_BLC);
    eval 'sub FW_BLC_SELF () {0x20e0;}' unless defined(&FW_BLC_SELF);
    eval 'sub MI_ARB_STATE () {0x20e4;}' unless defined(&MI_ARB_STATE);
    eval 'sub CACHE_MODE_0 () {0x2120;}' unless defined(&CACHE_MODE_0);
    eval 'sub CM0_MASK_SHIFT () {16;}' unless defined(&CM0_MASK_SHIFT);
    eval 'sub CM0_IZ_OPT_DISABLE () {(1<<6);}' unless defined(&CM0_IZ_OPT_DISABLE);
    eval 'sub CM0_ZR_OPT_DISABLE () {(1<<5);}' unless defined(&CM0_ZR_OPT_DISABLE);
    eval 'sub CM0_DEPTH_EVICT_DISABLE () {(1<<4);}' unless defined(&CM0_DEPTH_EVICT_DISABLE);
    eval 'sub CM0_COLOR_EVICT_DISABLE () {(1<<3);}' unless defined(&CM0_COLOR_EVICT_DISABLE);
    eval 'sub CM0_DEPTH_WRITE_DISABLE () {(1<<1);}' unless defined(&CM0_DEPTH_WRITE_DISABLE);
    eval 'sub CM0_RC_OP_FLUSH_DISABLE () {(1<<0);}' unless defined(&CM0_RC_OP_FLUSH_DISABLE);
    eval 'sub GFX_FLSH_CNTL () {0x2170;}' unless defined(&GFX_FLSH_CNTL);
    eval 'sub FBC_CFB_BASE () {0x3200;}' unless defined(&FBC_CFB_BASE);
    eval 'sub FBC_LL_BASE () {0x3204;}' unless defined(&FBC_LL_BASE);
    eval 'sub FBC_CONTROL () {0x3208;}' unless defined(&FBC_CONTROL);
    eval 'sub FBC_CTL_EN () {(1<<31);}' unless defined(&FBC_CTL_EN);
    eval 'sub FBC_CTL_PERIODIC () {(1<<30);}' unless defined(&FBC_CTL_PERIODIC);
    eval 'sub FBC_CTL_INTERVAL_SHIFT () {(16);}' unless defined(&FBC_CTL_INTERVAL_SHIFT);
    eval 'sub FBC_CTL_UNCOMPRESSIBLE () {(1<<14);}' unless defined(&FBC_CTL_UNCOMPRESSIBLE);
    eval 'sub FBC_CTL_STRIDE_SHIFT () {(5);}' unless defined(&FBC_CTL_STRIDE_SHIFT);
    eval 'sub FBC_CTL_FENCENO () {(1<<0);}' unless defined(&FBC_CTL_FENCENO);
    eval 'sub FBC_COMMAND () {0x320c;}' unless defined(&FBC_COMMAND);
    eval 'sub FBC_CMD_COMPRESS () {(1<<0);}' unless defined(&FBC_CMD_COMPRESS);
    eval 'sub FBC_STATUS () {0x3210;}' unless defined(&FBC_STATUS);
    eval 'sub FBC_STAT_COMPRESSING () {(1<<31);}' unless defined(&FBC_STAT_COMPRESSING);
    eval 'sub FBC_STAT_COMPRESSED () {(1<<30);}' unless defined(&FBC_STAT_COMPRESSED);
    eval 'sub FBC_STAT_MODIFIED () {(1<<29);}' unless defined(&FBC_STAT_MODIFIED);
    eval 'sub FBC_STAT_CURRENT_LINE () {(1<<0);}' unless defined(&FBC_STAT_CURRENT_LINE);
    eval 'sub FBC_CONTROL2 () {0x3214;}' unless defined(&FBC_CONTROL2);
    eval 'sub FBC_CTL_FENCE_DBL () {(0<<4);}' unless defined(&FBC_CTL_FENCE_DBL);
    eval 'sub FBC_CTL_IDLE_IMM () {(0<<2);}' unless defined(&FBC_CTL_IDLE_IMM);
    eval 'sub FBC_CTL_IDLE_FULL () {(1<<2);}' unless defined(&FBC_CTL_IDLE_FULL);
    eval 'sub FBC_CTL_IDLE_LINE () {(2<<2);}' unless defined(&FBC_CTL_IDLE_LINE);
    eval 'sub FBC_CTL_IDLE_DEBUG () {(3<<2);}' unless defined(&FBC_CTL_IDLE_DEBUG);
    eval 'sub FBC_CTL_CPU_FENCE () {(1<<1);}' unless defined(&FBC_CTL_CPU_FENCE);
    eval 'sub FBC_CTL_PLANEA () {(0<<0);}' unless defined(&FBC_CTL_PLANEA);
    eval 'sub FBC_CTL_PLANEB () {(1<<0);}' unless defined(&FBC_CTL_PLANEB);
    eval 'sub FBC_FENCE_OFF () {0x321b;}' unless defined(&FBC_FENCE_OFF);
    eval 'sub FBC_LL_SIZE () {(1536);}' unless defined(&FBC_LL_SIZE);
    eval 'sub GPIOA () {0x5010;}' unless defined(&GPIOA);
    eval 'sub GPIOB () {0x5014;}' unless defined(&GPIOB);
    eval 'sub GPIOC () {0x5018;}' unless defined(&GPIOC);
    eval 'sub GPIOD () {0x501c;}' unless defined(&GPIOD);
    eval 'sub GPIOE () {0x5020;}' unless defined(&GPIOE);
    eval 'sub GPIOF () {0x5024;}' unless defined(&GPIOF);
    eval 'sub GPIOG () {0x5028;}' unless defined(&GPIOG);
    eval 'sub GPIOH () {0x502c;}' unless defined(&GPIOH);
    eval 'sub GPIO_CLOCK_DIR_MASK () {(1<< 0);}' unless defined(&GPIO_CLOCK_DIR_MASK);
    eval 'sub GPIO_CLOCK_DIR_IN () {(0<< 1);}' unless defined(&GPIO_CLOCK_DIR_IN);
    eval 'sub GPIO_CLOCK_DIR_OUT () {(1<< 1);}' unless defined(&GPIO_CLOCK_DIR_OUT);
    eval 'sub GPIO_CLOCK_VAL_MASK () {(1<< 2);}' unless defined(&GPIO_CLOCK_VAL_MASK);
    eval 'sub GPIO_CLOCK_VAL_OUT () {(1<< 3);}' unless defined(&GPIO_CLOCK_VAL_OUT);
    eval 'sub GPIO_CLOCK_VAL_IN () {(1<< 4);}' unless defined(&GPIO_CLOCK_VAL_IN);
    eval 'sub GPIO_CLOCK_PULLUP_DISABLE () {(1<< 5);}' unless defined(&GPIO_CLOCK_PULLUP_DISABLE);
    eval 'sub GPIO_DATA_DIR_MASK () {(1<< 8);}' unless defined(&GPIO_DATA_DIR_MASK);
    eval 'sub GPIO_DATA_DIR_IN () {(0<< 9);}' unless defined(&GPIO_DATA_DIR_IN);
    eval 'sub GPIO_DATA_DIR_OUT () {(1<< 9);}' unless defined(&GPIO_DATA_DIR_OUT);
    eval 'sub GPIO_DATA_VAL_MASK () {(1<< 10);}' unless defined(&GPIO_DATA_VAL_MASK);
    eval 'sub GPIO_DATA_VAL_OUT () {(1<< 11);}' unless defined(&GPIO_DATA_VAL_OUT);
    eval 'sub GPIO_DATA_VAL_IN () {(1<< 12);}' unless defined(&GPIO_DATA_VAL_IN);
    eval 'sub GPIO_DATA_PULLUP_DISABLE () {(1<< 13);}' unless defined(&GPIO_DATA_PULLUP_DISABLE);
    eval 'sub VGA0 () {0x6000;}' unless defined(&VGA0);
    eval 'sub VGA1 () {0x6004;}' unless defined(&VGA1);
    eval 'sub VGA_PD () {0x6010;}' unless defined(&VGA_PD);
    eval 'sub VGA0_PD_P2_DIV_4 () {(1<< 7);}' unless defined(&VGA0_PD_P2_DIV_4);
    eval 'sub VGA0_PD_P1_DIV_2 () {(1<< 5);}' unless defined(&VGA0_PD_P1_DIV_2);
    eval 'sub VGA0_PD_P1_SHIFT () {0;}' unless defined(&VGA0_PD_P1_SHIFT);
    eval 'sub VGA0_PD_P1_MASK () {(0x1f << 0);}' unless defined(&VGA0_PD_P1_MASK);
    eval 'sub VGA1_PD_P2_DIV_4 () {(1<< 15);}' unless defined(&VGA1_PD_P2_DIV_4);
    eval 'sub VGA1_PD_P1_DIV_2 () {(1<< 13);}' unless defined(&VGA1_PD_P1_DIV_2);
    eval 'sub VGA1_PD_P1_SHIFT () {8;}' unless defined(&VGA1_PD_P1_SHIFT);
    eval 'sub VGA1_PD_P1_MASK () {(0x1f << 8);}' unless defined(&VGA1_PD_P1_MASK);
    eval 'sub DPLL_A () {0x6014;}' unless defined(&DPLL_A);
    eval 'sub DPLL_B () {0x6018;}' unless defined(&DPLL_B);
    eval 'sub DPLL_VCO_ENABLE () {(1<< 31);}' unless defined(&DPLL_VCO_ENABLE);
    eval 'sub DPLL_DVO_HIGH_SPEED () {(1<< 30);}' unless defined(&DPLL_DVO_HIGH_SPEED);
    eval 'sub DPLL_SYNCLOCK_ENABLE () {(1<< 29);}' unless defined(&DPLL_SYNCLOCK_ENABLE);
    eval 'sub DPLL_VGA_MODE_DIS () {(1<< 28);}' unless defined(&DPLL_VGA_MODE_DIS);
    eval 'sub DPLLB_MODE_DAC_SERIAL () {(1<< 26);}' unless defined(&DPLLB_MODE_DAC_SERIAL);
    eval 'sub DPLLB_MODE_LVDS () {(2<< 26);}' unless defined(&DPLLB_MODE_LVDS);
    eval 'sub DPLL_MODE_MASK () {(3<< 26);}' unless defined(&DPLL_MODE_MASK);
    eval 'sub DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 () {(0<< 24);}' unless defined(&DPLL_DAC_SERIAL_P2_CLOCK_DIV_10);
    eval 'sub DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 () {(1<< 24);}' unless defined(&DPLL_DAC_SERIAL_P2_CLOCK_DIV_5);
    eval 'sub DPLLB_LVDS_P2_CLOCK_DIV_14 () {(0<< 24);}' unless defined(&DPLLB_LVDS_P2_CLOCK_DIV_14);
    eval 'sub DPLLB_LVDS_P2_CLOCK_DIV_7 () {(1<< 24);}' unless defined(&DPLLB_LVDS_P2_CLOCK_DIV_7);
    eval 'sub DPLL_P2_CLOCK_DIV_MASK () {0x3000000;}' unless defined(&DPLL_P2_CLOCK_DIV_MASK);
    eval 'sub DPLL_FPA01_P1_POST_DIV_MASK () {0xff0000;}' unless defined(&DPLL_FPA01_P1_POST_DIV_MASK);
    eval 'sub I915_FIFO_UNDERRUN_STATUS () {(1<<31);}' unless defined(&I915_FIFO_UNDERRUN_STATUS);
    eval 'sub I915_CRC_ERROR_ENABLE () {(1<<29);}' unless defined(&I915_CRC_ERROR_ENABLE);
    eval 'sub I915_CRC_DONE_ENABLE () {(1<<28);}' unless defined(&I915_CRC_DONE_ENABLE);
    eval 'sub I915_GMBUS_EVENT_ENABLE () {(1<<27);}' unless defined(&I915_GMBUS_EVENT_ENABLE);
    eval 'sub I915_VSYNC_INTERRUPT_ENABLE () {(1<<25);}' unless defined(&I915_VSYNC_INTERRUPT_ENABLE);
    eval 'sub I915_DISPLAY_LINE_COMPARE_ENABLE () {(1<<24);}' unless defined(&I915_DISPLAY_LINE_COMPARE_ENABLE);
    eval 'sub I915_DPST_EVENT_ENABLE () {(1<<23);}' unless defined(&I915_DPST_EVENT_ENABLE);
    eval 'sub I915_LEGACY_BLC_EVENT_ENABLE () {(1<<22);}' unless defined(&I915_LEGACY_BLC_EVENT_ENABLE);
    eval 'sub I915_ODD_FIELD_INTERRUPT_ENABLE () {(1<<21);}' unless defined(&I915_ODD_FIELD_INTERRUPT_ENABLE);
    eval 'sub I915_EVEN_FIELD_INTERRUPT_ENABLE () {(1<<20);}' unless defined(&I915_EVEN_FIELD_INTERRUPT_ENABLE);
    eval 'sub I915_START_VBLANK_INTERRUPT_ENABLE () {(1<<18);}' unless defined(&I915_START_VBLANK_INTERRUPT_ENABLE);
    eval 'sub I915_VBLANK_INTERRUPT_ENABLE () {(1<<17);}' unless defined(&I915_VBLANK_INTERRUPT_ENABLE);
    eval 'sub I915_OVERLAY_UPDATED_ENABLE () {(1<<16);}' unless defined(&I915_OVERLAY_UPDATED_ENABLE);
    eval 'sub I915_CRC_ERROR_INTERRUPT_STATUS () {(1<<13);}' unless defined(&I915_CRC_ERROR_INTERRUPT_STATUS);
    eval 'sub I915_CRC_DONE_INTERRUPT_STATUS () {(1<<12);}' unless defined(&I915_CRC_DONE_INTERRUPT_STATUS);
    eval 'sub I915_GMBUS_INTERRUPT_STATUS () {(1<<11);}' unless defined(&I915_GMBUS_INTERRUPT_STATUS);
    eval 'sub I915_VSYNC_INTERRUPT_STATUS () {(1<<9);}' unless defined(&I915_VSYNC_INTERRUPT_STATUS);
    eval 'sub I915_DISPLAY_LINE_COMPARE_STATUS () {(1<<8);}' unless defined(&I915_DISPLAY_LINE_COMPARE_STATUS);
    eval 'sub I915_DPST_EVENT_STATUS () {(1<<7);}' unless defined(&I915_DPST_EVENT_STATUS);
    eval 'sub I915_LEGACY_BLC_EVENT_STATUS () {(1<<6);}' unless defined(&I915_LEGACY_BLC_EVENT_STATUS);
    eval 'sub I915_ODD_FIELD_INTERRUPT_STATUS () {(1<<5);}' unless defined(&I915_ODD_FIELD_INTERRUPT_STATUS);
    eval 'sub I915_EVEN_FIELD_INTERRUPT_STATUS () {(1<<4);}' unless defined(&I915_EVEN_FIELD_INTERRUPT_STATUS);
    eval 'sub I915_START_VBLANK_INTERRUPT_STATUS () {(1<<2);}' unless defined(&I915_START_VBLANK_INTERRUPT_STATUS);
    eval 'sub I915_VBLANK_INTERRUPT_STATUS () {(1<<1);}' unless defined(&I915_VBLANK_INTERRUPT_STATUS);
    eval 'sub I915_OVERLAY_UPDATED_STATUS () {(1<<0);}' unless defined(&I915_OVERLAY_UPDATED_STATUS);
    eval 'sub SRX_INDEX () {0x3c4;}' unless defined(&SRX_INDEX);
    eval 'sub SRX_DATA () {0x3c5;}' unless defined(&SRX_DATA);
    eval 'sub SR01 () {1;}' unless defined(&SR01);
    eval 'sub SR01_SCREEN_OFF () {(1<<5);}' unless defined(&SR01_SCREEN_OFF);
    eval 'sub PPCR () {0x61204;}' unless defined(&PPCR);
    eval 'sub PPCR_ON () {(1<<0);}' unless defined(&PPCR_ON);
    eval 'sub DVOB () {0x61140;}' unless defined(&DVOB);
    eval 'sub DVOB_ON () {(1<<31);}' unless defined(&DVOB_ON);
    eval 'sub DVOC () {0x61160;}' unless defined(&DVOC);
    eval 'sub DVOC_ON () {(1<<31);}' unless defined(&DVOC_ON);
    eval 'sub LVDS () {0x61180;}' unless defined(&LVDS);
    eval 'sub LVDS_ON () {(1<<31);}' unless defined(&LVDS_ON);
    eval 'sub ADPA () {0x61100;}' unless defined(&ADPA);
    eval 'sub ADPA_DPMS_MASK () {(~(3<<10));}' unless defined(&ADPA_DPMS_MASK);
    eval 'sub ADPA_DPMS_ON () {(0<<10);}' unless defined(&ADPA_DPMS_ON);
    eval 'sub ADPA_DPMS_SUSPEND () {(1<<10);}' unless defined(&ADPA_DPMS_SUSPEND);
    eval 'sub ADPA_DPMS_STANDBY () {(2<<10);}' unless defined(&ADPA_DPMS_STANDBY);
    eval 'sub ADPA_DPMS_OFF () {(3<<10);}' unless defined(&ADPA_DPMS_OFF);
    eval 'sub RING_TAIL () {0x;}' unless defined(&RING_TAIL);
    eval 'sub TAIL_ADDR () {0x1ffff8;}' unless defined(&TAIL_ADDR);
    eval 'sub RING_HEAD () {0x4;}' unless defined(&RING_HEAD);
    eval 'sub HEAD_WRAP_COUNT () {0xffe00000;}' unless defined(&HEAD_WRAP_COUNT);
    eval 'sub HEAD_WRAP_ONE () {0x200000;}' unless defined(&HEAD_WRAP_ONE);
    eval 'sub HEAD_ADDR () {0x1ffffc;}' unless defined(&HEAD_ADDR);
    eval 'sub RING_START () {0x8;}' unless defined(&RING_START);
    eval 'sub START_ADDR () {0xfffff000;}' unless defined(&START_ADDR);
    eval 'sub RING_LEN () {0xc;}' unless defined(&RING_LEN);
    eval 'sub RING_NR_PAGES () {0x1ff000;}' unless defined(&RING_NR_PAGES);
    eval 'sub RING_REPORT_MASK () {0x6;}' unless defined(&RING_REPORT_MASK);
    eval 'sub RING_REPORT_64K () {0x2;}' unless defined(&RING_REPORT_64K);
    eval 'sub RING_REPORT_128K () {0x4;}' unless defined(&RING_REPORT_128K);
    eval 'sub RING_NO_REPORT () {0x;}' unless defined(&RING_NO_REPORT);
    eval 'sub RING_VALID_MASK () {0x1;}' unless defined(&RING_VALID_MASK);
    eval 'sub RING_VALID () {0x1;}' unless defined(&RING_VALID);
    eval 'sub RING_INVALID () {0x;}' unless defined(&RING_INVALID);
    eval 'sub DPLL_FPA01_P1_POST_DIV_MASK_I830 () {0x1f0000;}' unless defined(&DPLL_FPA01_P1_POST_DIV_MASK_I830);
    eval 'sub DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS () {0x3f0000;}' unless defined(&DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS);
    eval 'sub DPLL_FPA01_P1_POST_DIV_SHIFT () {16;}' unless defined(&DPLL_FPA01_P1_POST_DIV_SHIFT);
    eval 'sub PLL_P2_DIVIDE_BY_4 () {(1<< 23);}' unless defined(&PLL_P2_DIVIDE_BY_4);
    eval 'sub PLL_P1_DIVIDE_BY_TWO () {(1<< 21);}' unless defined(&PLL_P1_DIVIDE_BY_TWO);
    eval 'sub PLL_REF_INPUT_DREFCLK () {(0<< 13);}' unless defined(&PLL_REF_INPUT_DREFCLK);
    eval 'sub PLL_REF_INPUT_TVCLKINA () {(1<< 13);}' unless defined(&PLL_REF_INPUT_TVCLKINA);
    eval 'sub PLL_REF_INPUT_TVCLKINBC () {(2<< 13);}' unless defined(&PLL_REF_INPUT_TVCLKINBC);
    eval 'sub PLLB_REF_INPUT_SPREADSPECTRUMIN () {(3<< 13);}' unless defined(&PLLB_REF_INPUT_SPREADSPECTRUMIN);
    eval 'sub PLL_REF_INPUT_MASK () {(3<< 13);}' unless defined(&PLL_REF_INPUT_MASK);
    eval 'sub PLL_LOAD_PULSE_PHASE_SHIFT () {9;}' unless defined(&PLL_LOAD_PULSE_PHASE_SHIFT);
    eval 'sub PLL_LOAD_PULSE_PHASE_MASK () {(0xf <<  &PLL_LOAD_PULSE_PHASE_SHIFT);}' unless defined(&PLL_LOAD_PULSE_PHASE_MASK);
    eval 'sub DISPLAY_RATE_SELECT_FPA1 () {(1<< 8);}' unless defined(&DISPLAY_RATE_SELECT_FPA1);
    eval 'sub SDVO_MULTIPLIER_MASK () {0xff;}' unless defined(&SDVO_MULTIPLIER_MASK);
    eval 'sub SDVO_MULTIPLIER_SHIFT_HIRES () {4;}' unless defined(&SDVO_MULTIPLIER_SHIFT_HIRES);
    eval 'sub SDVO_MULTIPLIER_SHIFT_VGA () {0;}' unless defined(&SDVO_MULTIPLIER_SHIFT_VGA);
    eval 'sub DPLL_A_MD () {0x601c;}' unless defined(&DPLL_A_MD);
    eval 'sub DPLL_MD_UDI_DIVIDER_MASK () {0x3f000000;}' unless defined(&DPLL_MD_UDI_DIVIDER_MASK);
    eval 'sub DPLL_MD_UDI_DIVIDER_SHIFT () {24;}' unless defined(&DPLL_MD_UDI_DIVIDER_SHIFT);
    eval 'sub DPLL_MD_VGA_UDI_DIVIDER_MASK () {0x3f0000;}' unless defined(&DPLL_MD_VGA_UDI_DIVIDER_MASK);
    eval 'sub DPLL_MD_VGA_UDI_DIVIDER_SHIFT () {16;}' unless defined(&DPLL_MD_VGA_UDI_DIVIDER_SHIFT);
    eval 'sub DPLL_MD_UDI_MULTIPLIER_MASK () {0x3f00;}' unless defined(&DPLL_MD_UDI_MULTIPLIER_MASK);
    eval 'sub DPLL_MD_UDI_MULTIPLIER_SHIFT () {8;}' unless defined(&DPLL_MD_UDI_MULTIPLIER_SHIFT);
    eval 'sub DPLL_MD_VGA_UDI_MULTIPLIER_MASK () {0x3f;}' unless defined(&DPLL_MD_VGA_UDI_MULTIPLIER_MASK);
    eval 'sub DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT () {0;}' unless defined(&DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT);
    eval 'sub DPLL_B_MD () {0x6020;}' unless defined(&DPLL_B_MD);
    eval 'sub FPA0 () {0x6040;}' unless defined(&FPA0);
    eval 'sub FPA1 () {0x6044;}' unless defined(&FPA1);
    eval 'sub FPB0 () {0x6048;}' unless defined(&FPB0);
    eval 'sub FPB1 () {0x604c;}' unless defined(&FPB1);
    eval 'sub FP_N_DIV_MASK () {0x3f0000;}' unless defined(&FP_N_DIV_MASK);
    eval 'sub FP_N_DIV_SHIFT () {16;}' unless defined(&FP_N_DIV_SHIFT);
    eval 'sub FP_M1_DIV_MASK () {0x3f00;}' unless defined(&FP_M1_DIV_MASK);
    eval 'sub FP_M1_DIV_SHIFT () {8;}' unless defined(&FP_M1_DIV_SHIFT);
    eval 'sub FP_M2_DIV_MASK () {0x3f;}' unless defined(&FP_M2_DIV_MASK);
    eval 'sub FP_M2_DIV_SHIFT () {0;}' unless defined(&FP_M2_DIV_SHIFT);
    eval 'sub DPLL_TEST () {0x606c;}' unless defined(&DPLL_TEST);
    eval 'sub DPLLB_TEST_SDVO_DIV_1 () {(0<< 22);}' unless defined(&DPLLB_TEST_SDVO_DIV_1);
    eval 'sub DPLLB_TEST_SDVO_DIV_2 () {(1<< 22);}' unless defined(&DPLLB_TEST_SDVO_DIV_2);
    eval 'sub DPLLB_TEST_SDVO_DIV_4 () {(2<< 22);}' unless defined(&DPLLB_TEST_SDVO_DIV_4);
    eval 'sub DPLLB_TEST_SDVO_DIV_MASK () {(3<< 22);}' unless defined(&DPLLB_TEST_SDVO_DIV_MASK);
    eval 'sub DPLLB_TEST_N_BYPASS () {(1<< 19);}' unless defined(&DPLLB_TEST_N_BYPASS);
    eval 'sub DPLLB_TEST_M_BYPASS () {(1<< 18);}' unless defined(&DPLLB_TEST_M_BYPASS);
    eval 'sub DPLLB_INPUT_BUFFER_ENABLE () {(1<< 16);}' unless defined(&DPLLB_INPUT_BUFFER_ENABLE);
    eval 'sub DPLLA_TEST_N_BYPASS () {(1<< 3);}' unless defined(&DPLLA_TEST_N_BYPASS);
    eval 'sub DPLLA_TEST_M_BYPASS () {(1<< 2);}' unless defined(&DPLLA_TEST_M_BYPASS);
    eval 'sub DPLLA_INPUT_BUFFER_ENABLE () {(1<< 0);}' unless defined(&DPLLA_INPUT_BUFFER_ENABLE);
    eval 'sub D_STATE () {0x6104;}' unless defined(&D_STATE);
    eval 'sub CG_2D_DIS () {0x6200;}' unless defined(&CG_2D_DIS);
    eval 'sub CG_3D_DIS () {0x6204;}' unless defined(&CG_3D_DIS);
    eval 'sub PALETTE_A () {0xa000;}' unless defined(&PALETTE_A);
    eval 'sub PALETTE_B () {0xa800;}' unless defined(&PALETTE_B);
    eval 'sub OVADD () {0x30000;}' unless defined(&OVADD);
    eval 'sub DOVSTA () {0x30008;}' unless defined(&DOVSTA);
    eval 'sub OC_BUF () {(0x3<<20);}' unless defined(&OC_BUF);
    eval 'sub OGAMC5 () {0x30010;}' unless defined(&OGAMC5);
    eval 'sub OGAMC4 () {0x30014;}' unless defined(&OGAMC4);
    eval 'sub OGAMC3 () {0x30018;}' unless defined(&OGAMC3);
    eval 'sub OGAMC2 () {0x3001c;}' unless defined(&OGAMC2);
    eval 'sub OGAMC1 () {0x30020;}' unless defined(&OGAMC1);
    eval 'sub OGAMC0 () {0x30024;}' unless defined(&OGAMC0);
    eval 'sub HTOTAL_A () {0x60000;}' unless defined(&HTOTAL_A);
    eval 'sub HBLANK_A () {0x60004;}' unless defined(&HBLANK_A);
    eval 'sub HSYNC_A () {0x60008;}' unless defined(&HSYNC_A);
    eval 'sub VTOTAL_A () {0x6000c;}' unless defined(&VTOTAL_A);
    eval 'sub VBLANK_A () {0x60010;}' unless defined(&VBLANK_A);
    eval 'sub VSYNC_A () {0x60014;}' unless defined(&VSYNC_A);
    eval 'sub PIPEASRC () {0x6001c;}' unless defined(&PIPEASRC);
    eval 'sub BCLRPAT_A () {0x60020;}' unless defined(&BCLRPAT_A);
    eval 'sub HTOTAL_B () {0x61000;}' unless defined(&HTOTAL_B);
    eval 'sub HBLANK_B () {0x61004;}' unless defined(&HBLANK_B);
    eval 'sub HSYNC_B () {0x61008;}' unless defined(&HSYNC_B);
    eval 'sub VTOTAL_B () {0x6100c;}' unless defined(&VTOTAL_B);
    eval 'sub VBLANK_B () {0x61010;}' unless defined(&VBLANK_B);
    eval 'sub VSYNC_B () {0x61014;}' unless defined(&VSYNC_B);
    eval 'sub PIPEBSRC () {0x6101c;}' unless defined(&PIPEBSRC);
    eval 'sub BCLRPAT_B () {0x61020;}' unless defined(&BCLRPAT_B);
    eval 'sub ADPA () {0x61100;}' unless defined(&ADPA);
    eval 'sub ADPA_DAC_ENABLE () {(1<<31);}' unless defined(&ADPA_DAC_ENABLE);
    eval 'sub ADPA_DAC_DISABLE () {0;}' unless defined(&ADPA_DAC_DISABLE);
    eval 'sub ADPA_PIPE_SELECT_MASK () {(1<<30);}' unless defined(&ADPA_PIPE_SELECT_MASK);
    eval 'sub ADPA_PIPE_A_SELECT () {0;}' unless defined(&ADPA_PIPE_A_SELECT);
    eval 'sub ADPA_PIPE_B_SELECT () {(1<<30);}' unless defined(&ADPA_PIPE_B_SELECT);
    eval 'sub ADPA_USE_VGA_HVPOLARITY () {(1<<15);}' unless defined(&ADPA_USE_VGA_HVPOLARITY);
    eval 'sub ADPA_SETS_HVPOLARITY () {0;}' unless defined(&ADPA_SETS_HVPOLARITY);
    eval 'sub ADPA_VSYNC_CNTL_DISABLE () {(1<<11);}' unless defined(&ADPA_VSYNC_CNTL_DISABLE);
    eval 'sub ADPA_VSYNC_CNTL_ENABLE () {0;}' unless defined(&ADPA_VSYNC_CNTL_ENABLE);
    eval 'sub ADPA_HSYNC_CNTL_DISABLE () {(1<<10);}' unless defined(&ADPA_HSYNC_CNTL_DISABLE);
    eval 'sub ADPA_HSYNC_CNTL_ENABLE () {0;}' unless defined(&ADPA_HSYNC_CNTL_ENABLE);
    eval 'sub ADPA_VSYNC_ACTIVE_HIGH () {(1<<4);}' unless defined(&ADPA_VSYNC_ACTIVE_HIGH);
    eval 'sub ADPA_VSYNC_ACTIVE_LOW () {0;}' unless defined(&ADPA_VSYNC_ACTIVE_LOW);
    eval 'sub ADPA_HSYNC_ACTIVE_HIGH () {(1<<3);}' unless defined(&ADPA_HSYNC_ACTIVE_HIGH);
    eval 'sub ADPA_HSYNC_ACTIVE_LOW () {0;}' unless defined(&ADPA_HSYNC_ACTIVE_LOW);
    eval 'sub ADPA_DPMS_MASK () {(~(3<<10));}' unless defined(&ADPA_DPMS_MASK);
    eval 'sub ADPA_DPMS_ON () {(0<<10);}' unless defined(&ADPA_DPMS_ON);
    eval 'sub ADPA_DPMS_SUSPEND () {(1<<10);}' unless defined(&ADPA_DPMS_SUSPEND);
    eval 'sub ADPA_DPMS_STANDBY () {(2<<10);}' unless defined(&ADPA_DPMS_STANDBY);
    eval 'sub ADPA_DPMS_OFF () {(3<<10);}' unless defined(&ADPA_DPMS_OFF);
    eval 'sub PORT_HOTPLUG_EN () {0x61110;}' unless defined(&PORT_HOTPLUG_EN);
    eval 'sub SDVOB_HOTPLUG_INT_EN () {(1<< 26);}' unless defined(&SDVOB_HOTPLUG_INT_EN);
    eval 'sub SDVOC_HOTPLUG_INT_EN () {(1<< 25);}' unless defined(&SDVOC_HOTPLUG_INT_EN);
    eval 'sub TV_HOTPLUG_INT_EN () {(1<< 18);}' unless defined(&TV_HOTPLUG_INT_EN);
    eval 'sub CRT_HOTPLUG_INT_EN () {(1<< 9);}' unless defined(&CRT_HOTPLUG_INT_EN);
    eval 'sub CRT_HOTPLUG_FORCE_DETECT () {(1<< 3);}' unless defined(&CRT_HOTPLUG_FORCE_DETECT);
    eval 'sub PORT_HOTPLUG_STAT () {0x61114;}' unless defined(&PORT_HOTPLUG_STAT);
    eval 'sub CRT_HOTPLUG_INT_STATUS () {(1<< 11);}' unless defined(&CRT_HOTPLUG_INT_STATUS);
    eval 'sub TV_HOTPLUG_INT_STATUS () {(1<< 10);}' unless defined(&TV_HOTPLUG_INT_STATUS);
    eval 'sub CRT_HOTPLUG_MONITOR_MASK () {(3<< 8);}' unless defined(&CRT_HOTPLUG_MONITOR_MASK);
    eval 'sub CRT_HOTPLUG_MONITOR_COLOR () {(3<< 8);}' unless defined(&CRT_HOTPLUG_MONITOR_COLOR);
    eval 'sub CRT_HOTPLUG_MONITOR_MONO () {(2<< 8);}' unless defined(&CRT_HOTPLUG_MONITOR_MONO);
    eval 'sub CRT_HOTPLUG_MONITOR_NONE () {(0<< 8);}' unless defined(&CRT_HOTPLUG_MONITOR_NONE);
    eval 'sub SDVOC_HOTPLUG_INT_STATUS () {(1<< 7);}' unless defined(&SDVOC_HOTPLUG_INT_STATUS);
    eval 'sub SDVOB_HOTPLUG_INT_STATUS () {(1<< 6);}' unless defined(&SDVOB_HOTPLUG_INT_STATUS);
    eval 'sub SDVOB () {0x61140;}' unless defined(&SDVOB);
    eval 'sub SDVOC () {0x61160;}' unless defined(&SDVOC);
    eval 'sub SDVO_ENABLE () {(1<< 31);}' unless defined(&SDVO_ENABLE);
    eval 'sub SDVO_PIPE_B_SELECT () {(1<< 30);}' unless defined(&SDVO_PIPE_B_SELECT);
    eval 'sub SDVO_STALL_SELECT () {(1<< 29);}' unless defined(&SDVO_STALL_SELECT);
    eval 'sub SDVO_INTERRUPT_ENABLE () {(1<< 26);}' unless defined(&SDVO_INTERRUPT_ENABLE);
    eval 'sub SDVO_PORT_MULTIPLY_MASK () {(7<< 23);}' unless defined(&SDVO_PORT_MULTIPLY_MASK);
    eval 'sub SDVO_PORT_MULTIPLY_SHIFT () {23;}' unless defined(&SDVO_PORT_MULTIPLY_SHIFT);
    eval 'sub SDVO_PHASE_SELECT_MASK () {(15<< 19);}' unless defined(&SDVO_PHASE_SELECT_MASK);
    eval 'sub SDVO_PHASE_SELECT_DEFAULT () {(6<< 19);}' unless defined(&SDVO_PHASE_SELECT_DEFAULT);
    eval 'sub SDVO_CLOCK_OUTPUT_INVERT () {(1<< 18);}' unless defined(&SDVO_CLOCK_OUTPUT_INVERT);
    eval 'sub SDVOC_GANG_MODE () {(1<< 16);}' unless defined(&SDVOC_GANG_MODE);
    eval 'sub SDVO_BORDER_ENABLE () {(1<< 7);}' unless defined(&SDVO_BORDER_ENABLE);
    eval 'sub SDVOB_PCIE_CONCURRENCY () {(1<< 3);}' unless defined(&SDVOB_PCIE_CONCURRENCY);
    eval 'sub SDVO_DETECTED () {(1<< 2);}' unless defined(&SDVO_DETECTED);
    eval 'sub SDVOB_PRESERVE_MASK () {((1<< 17) | (1<< 16) | (1<< 14) | (1<< 26));}' unless defined(&SDVOB_PRESERVE_MASK);
    eval 'sub SDVOC_PRESERVE_MASK () {((1<< 17) | (1<< 26));}' unless defined(&SDVOC_PRESERVE_MASK);
    eval 'sub DVOA () {0x61120;}' unless defined(&DVOA);
    eval 'sub DVOB () {0x61140;}' unless defined(&DVOB);
    eval 'sub DVOC () {0x61160;}' unless defined(&DVOC);
    eval 'sub DVO_ENABLE () {(1<< 31);}' unless defined(&DVO_ENABLE);
    eval 'sub DVO_PIPE_B_SELECT () {(1<< 30);}' unless defined(&DVO_PIPE_B_SELECT);
    eval 'sub DVO_PIPE_STALL_UNUSED () {(0<< 28);}' unless defined(&DVO_PIPE_STALL_UNUSED);
    eval 'sub DVO_PIPE_STALL () {(1<< 28);}' unless defined(&DVO_PIPE_STALL);
    eval 'sub DVO_PIPE_STALL_TV () {(2<< 28);}' unless defined(&DVO_PIPE_STALL_TV);
    eval 'sub DVO_PIPE_STALL_MASK () {(3<< 28);}' unless defined(&DVO_PIPE_STALL_MASK);
    eval 'sub DVO_USE_VGA_SYNC () {(1<< 15);}' unless defined(&DVO_USE_VGA_SYNC);
    eval 'sub DVO_DATA_ORDER_I740 () {(0<< 14);}' unless defined(&DVO_DATA_ORDER_I740);
    eval 'sub DVO_DATA_ORDER_FP () {(1<< 14);}' unless defined(&DVO_DATA_ORDER_FP);
    eval 'sub DVO_VSYNC_DISABLE () {(1<< 11);}' unless defined(&DVO_VSYNC_DISABLE);
    eval 'sub DVO_HSYNC_DISABLE () {(1<< 10);}' unless defined(&DVO_HSYNC_DISABLE);
    eval 'sub DVO_VSYNC_TRISTATE () {(1<< 9);}' unless defined(&DVO_VSYNC_TRISTATE);
    eval 'sub DVO_HSYNC_TRISTATE () {(1<< 8);}' unless defined(&DVO_HSYNC_TRISTATE);
    eval 'sub DVO_BORDER_ENABLE () {(1<< 7);}' unless defined(&DVO_BORDER_ENABLE);
    eval 'sub DVO_DATA_ORDER_GBRG () {(1<< 6);}' unless defined(&DVO_DATA_ORDER_GBRG);
    eval 'sub DVO_DATA_ORDER_RGGB () {(0<< 6);}' unless defined(&DVO_DATA_ORDER_RGGB);
    eval 'sub DVO_DATA_ORDER_GBRG_ERRATA () {(0<< 6);}' unless defined(&DVO_DATA_ORDER_GBRG_ERRATA);
    eval 'sub DVO_DATA_ORDER_RGGB_ERRATA () {(1<< 6);}' unless defined(&DVO_DATA_ORDER_RGGB_ERRATA);
    eval 'sub DVO_VSYNC_ACTIVE_HIGH () {(1<< 4);}' unless defined(&DVO_VSYNC_ACTIVE_HIGH);
    eval 'sub DVO_HSYNC_ACTIVE_HIGH () {(1<< 3);}' unless defined(&DVO_HSYNC_ACTIVE_HIGH);
    eval 'sub DVO_BLANK_ACTIVE_HIGH () {(1<< 2);}' unless defined(&DVO_BLANK_ACTIVE_HIGH);
    eval 'sub DVO_OUTPUT_CSTATE_PIXELS () {(1<< 1);}' unless defined(&DVO_OUTPUT_CSTATE_PIXELS);
    eval 'sub DVO_OUTPUT_SOURCE_SIZE_PIXELS () {(1<< 0);}' unless defined(&DVO_OUTPUT_SOURCE_SIZE_PIXELS);
    eval 'sub DVO_PRESERVE_MASK () {(0x7<<24);}' unless defined(&DVO_PRESERVE_MASK);
    eval 'sub DVOA_SRCDIM () {0x61124;}' unless defined(&DVOA_SRCDIM);
    eval 'sub DVOB_SRCDIM () {0x61144;}' unless defined(&DVOB_SRCDIM);
    eval 'sub DVOC_SRCDIM () {0x61164;}' unless defined(&DVOC_SRCDIM);
    eval 'sub DVO_SRCDIM_HORIZONTAL_SHIFT () {12;}' unless defined(&DVO_SRCDIM_HORIZONTAL_SHIFT);
    eval 'sub DVO_SRCDIM_VERTICAL_SHIFT () {0;}' unless defined(&DVO_SRCDIM_VERTICAL_SHIFT);
    eval 'sub LVDS () {0x61180;}' unless defined(&LVDS);
    eval 'sub LVDS_PORT_EN () {(1<< 31);}' unless defined(&LVDS_PORT_EN);
    eval 'sub LVDS_PIPEB_SELECT () {(1<< 30);}' unless defined(&LVDS_PIPEB_SELECT);
    eval 'sub LVDS_A0A2_CLKA_POWER_MASK () {(3<< 8);}' unless defined(&LVDS_A0A2_CLKA_POWER_MASK);
    eval 'sub LVDS_A0A2_CLKA_POWER_DOWN () {(0<< 8);}' unless defined(&LVDS_A0A2_CLKA_POWER_DOWN);
    eval 'sub LVDS_A0A2_CLKA_POWER_UP () {(3<< 8);}' unless defined(&LVDS_A0A2_CLKA_POWER_UP);
    eval 'sub LVDS_A3_POWER_MASK () {(3<< 6);}' unless defined(&LVDS_A3_POWER_MASK);
    eval 'sub LVDS_A3_POWER_DOWN () {(0<< 6);}' unless defined(&LVDS_A3_POWER_DOWN);
    eval 'sub LVDS_A3_POWER_UP () {(3<< 6);}' unless defined(&LVDS_A3_POWER_UP);
    eval 'sub LVDS_CLKB_POWER_MASK () {(3<< 4);}' unless defined(&LVDS_CLKB_POWER_MASK);
    eval 'sub LVDS_CLKB_POWER_DOWN () {(0<< 4);}' unless defined(&LVDS_CLKB_POWER_DOWN);
    eval 'sub LVDS_CLKB_POWER_UP () {(3<< 4);}' unless defined(&LVDS_CLKB_POWER_UP);
    eval 'sub LVDS_B0B3_POWER_MASK () {(3<< 2);}' unless defined(&LVDS_B0B3_POWER_MASK);
    eval 'sub LVDS_B0B3_POWER_DOWN () {(0<< 2);}' unless defined(&LVDS_B0B3_POWER_DOWN);
    eval 'sub LVDS_B0B3_POWER_UP () {(3<< 2);}' unless defined(&LVDS_B0B3_POWER_UP);
    eval 'sub PP_STATUS () {0x61200;}' unless defined(&PP_STATUS);
    eval 'sub PP_ON () {(1<< 31);}' unless defined(&PP_ON);
    eval 'sub PP_READY () {(1<< 30);}' unless defined(&PP_READY);
    eval 'sub PP_SEQUENCE_NONE () {(0<< 28);}' unless defined(&PP_SEQUENCE_NONE);
    eval 'sub PP_SEQUENCE_ON () {(1<< 28);}' unless defined(&PP_SEQUENCE_ON);
    eval 'sub PP_SEQUENCE_OFF () {(2<< 28);}' unless defined(&PP_SEQUENCE_OFF);
    eval 'sub PP_SEQUENCE_MASK () {0x30000000;}' unless defined(&PP_SEQUENCE_MASK);
    eval 'sub PP_CONTROL () {0x61204;}' unless defined(&PP_CONTROL);
    eval 'sub POWER_TARGET_ON () {(1<< 0);}' unless defined(&POWER_TARGET_ON);
    eval 'sub PP_ON_DELAYS () {0x61208;}' unless defined(&PP_ON_DELAYS);
    eval 'sub PP_OFF_DELAYS () {0x6120c;}' unless defined(&PP_OFF_DELAYS);
    eval 'sub PP_DIVISOR () {0x61210;}' unless defined(&PP_DIVISOR);
    eval 'sub PFIT_CONTROL () {0x61230;}' unless defined(&PFIT_CONTROL);
    eval 'sub PFIT_ENABLE () {(1<< 31);}' unless defined(&PFIT_ENABLE);
    eval 'sub PFIT_PIPE_MASK () {(3<< 29);}' unless defined(&PFIT_PIPE_MASK);
    eval 'sub PFIT_PIPE_SHIFT () {29;}' unless defined(&PFIT_PIPE_SHIFT);
    eval 'sub VERT_INTERP_DISABLE () {(0<< 10);}' unless defined(&VERT_INTERP_DISABLE);
    eval 'sub VERT_INTERP_BILINEAR () {(1<< 10);}' unless defined(&VERT_INTERP_BILINEAR);
    eval 'sub VERT_INTERP_MASK () {(3<< 10);}' unless defined(&VERT_INTERP_MASK);
    eval 'sub VERT_AUTO_SCALE () {(1<< 9);}' unless defined(&VERT_AUTO_SCALE);
    eval 'sub HORIZ_INTERP_DISABLE () {(0<< 6);}' unless defined(&HORIZ_INTERP_DISABLE);
    eval 'sub HORIZ_INTERP_BILINEAR () {(1<< 6);}' unless defined(&HORIZ_INTERP_BILINEAR);
    eval 'sub HORIZ_INTERP_MASK () {(3<< 6);}' unless defined(&HORIZ_INTERP_MASK);
    eval 'sub HORIZ_AUTO_SCALE () {(1<< 5);}' unless defined(&HORIZ_AUTO_SCALE);
    eval 'sub PANEL_8TO6_DITHER_ENABLE () {(1<< 3);}' unless defined(&PANEL_8TO6_DITHER_ENABLE);
    eval 'sub PFIT_PGM_RATIOS () {0x61234;}' unless defined(&PFIT_PGM_RATIOS);
    eval 'sub PFIT_VERT_SCALE_MASK () {0xfff00000;}' unless defined(&PFIT_VERT_SCALE_MASK);
    eval 'sub PFIT_HORIZ_SCALE_MASK () {0xfff0;}' unless defined(&PFIT_HORIZ_SCALE_MASK);
    eval 'sub PFIT_AUTO_RATIOS () {0x61238;}' unless defined(&PFIT_AUTO_RATIOS);
    eval 'sub BLC_PWM_CTL () {0x61254;}' unless defined(&BLC_PWM_CTL);
    eval 'sub BACKLIGHT_MODULATION_FREQ_SHIFT () {(17);}' unless defined(&BACKLIGHT_MODULATION_FREQ_SHIFT);
    eval 'sub BLC_PWM_CTL2 () {0x61250;}' unless defined(&BLC_PWM_CTL2);
    eval 'sub BACKLIGHT_MODULATION_FREQ_MASK () {(0x7fff << 17);}' unless defined(&BACKLIGHT_MODULATION_FREQ_MASK);
    eval 'sub BLM_LEGACY_MODE () {(1<< 16);}' unless defined(&BLM_LEGACY_MODE);
    eval 'sub BACKLIGHT_DUTY_CYCLE_SHIFT () {(0);}' unless defined(&BACKLIGHT_DUTY_CYCLE_SHIFT);
    eval 'sub BACKLIGHT_DUTY_CYCLE_MASK () {(0xffff);}' unless defined(&BACKLIGHT_DUTY_CYCLE_MASK);
    eval 'sub TV_CTL () {0x68000;}' unless defined(&TV_CTL);
    eval 'sub TV_ENC_ENABLE () {(1<< 31);}' unless defined(&TV_ENC_ENABLE);
    eval 'sub TV_ENC_PIPEB_SELECT () {(1<< 30);}' unless defined(&TV_ENC_PIPEB_SELECT);
    eval 'sub TV_ENC_OUTPUT_COMPOSITE () {(0<< 28);}' unless defined(&TV_ENC_OUTPUT_COMPOSITE);
    eval 'sub TV_ENC_OUTPUT_SVIDEO () {(1<< 28);}' unless defined(&TV_ENC_OUTPUT_SVIDEO);
    eval 'sub TV_ENC_OUTPUT_COMPONENT () {(2<< 28);}' unless defined(&TV_ENC_OUTPUT_COMPONENT);
    eval 'sub TV_ENC_OUTPUT_SVIDEO_COMPOSITE () {(3<< 28);}' unless defined(&TV_ENC_OUTPUT_SVIDEO_COMPOSITE);
    eval 'sub TV_TRILEVEL_SYNC () {(1<< 21);}' unless defined(&TV_TRILEVEL_SYNC);
    eval 'sub TV_SLOW_SYNC () {(1<< 20);}' unless defined(&TV_SLOW_SYNC);
    eval 'sub TV_OVERSAMPLE_4X () {(0<< 18);}' unless defined(&TV_OVERSAMPLE_4X);
    eval 'sub TV_OVERSAMPLE_2X () {(1<< 18);}' unless defined(&TV_OVERSAMPLE_2X);
    eval 'sub TV_OVERSAMPLE_NONE () {(2<< 18);}' unless defined(&TV_OVERSAMPLE_NONE);
    eval 'sub TV_OVERSAMPLE_8X () {(3<< 18);}' unless defined(&TV_OVERSAMPLE_8X);
    eval 'sub TV_PROGRESSIVE () {(1<< 17);}' unless defined(&TV_PROGRESSIVE);
    eval 'sub TV_PAL_BURST () {(1<< 16);}' unless defined(&TV_PAL_BURST);
    eval 'sub TV_YC_SKEW_MASK () {(7<< 12);}' unless defined(&TV_YC_SKEW_MASK);
    eval 'sub TV_ENC_SDP_FIX () {(1<< 11);}' unless defined(&TV_ENC_SDP_FIX);
    eval 'sub TV_ENC_C0_FIX () {(1<< 10);}' unless defined(&TV_ENC_C0_FIX);
    eval 'sub TV_CTL_SAVE () {((3<< 8) | (3<< 6));}' unless defined(&TV_CTL_SAVE);
    eval 'sub TV_FUSE_STATE_MASK () {(3<< 4);}' unless defined(&TV_FUSE_STATE_MASK);
    eval 'sub TV_FUSE_STATE_ENABLED () {(0<< 4);}' unless defined(&TV_FUSE_STATE_ENABLED);
    eval 'sub TV_FUSE_STATE_NO_MACROVISION () {(1<< 4);}' unless defined(&TV_FUSE_STATE_NO_MACROVISION);
    eval 'sub TV_FUSE_STATE_DISABLED () {(2<< 4);}' unless defined(&TV_FUSE_STATE_DISABLED);
    eval 'sub TV_TEST_MODE_NORMAL () {(0<< 0);}' unless defined(&TV_TEST_MODE_NORMAL);
    eval 'sub TV_TEST_MODE_PATTERN_1 () {(1<< 0);}' unless defined(&TV_TEST_MODE_PATTERN_1);
    eval 'sub TV_TEST_MODE_PATTERN_2 () {(2<< 0);}' unless defined(&TV_TEST_MODE_PATTERN_2);
    eval 'sub TV_TEST_MODE_PATTERN_3 () {(3<< 0);}' unless defined(&TV_TEST_MODE_PATTERN_3);
    eval 'sub TV_TEST_MODE_PATTERN_4 () {(4<< 0);}' unless defined(&TV_TEST_MODE_PATTERN_4);
    eval 'sub TV_TEST_MODE_PATTERN_5 () {(5<< 0);}' unless defined(&TV_TEST_MODE_PATTERN_5);
    eval 'sub TV_TEST_MODE_MONITOR_DETECT () {(7<< 0);}' unless defined(&TV_TEST_MODE_MONITOR_DETECT);
    eval 'sub TV_TEST_MODE_MASK () {(7<< 0);}' unless defined(&TV_TEST_MODE_MASK);
    eval 'sub TV_DAC () {0x68004;}' unless defined(&TV_DAC);
    eval 'sub TVDAC_STATE_CHG () {(1<< 31);}' unless defined(&TVDAC_STATE_CHG);
    eval 'sub TVDAC_SENSE_MASK () {(7<< 28);}' unless defined(&TVDAC_SENSE_MASK);
    eval 'sub TVDAC_A_SENSE () {(1<< 30);}' unless defined(&TVDAC_A_SENSE);
    eval 'sub TVDAC_B_SENSE () {(1<< 29);}' unless defined(&TVDAC_B_SENSE);
    eval 'sub TVDAC_C_SENSE () {(1<< 28);}' unless defined(&TVDAC_C_SENSE);
    eval 'sub TVDAC_STATE_CHG_EN () {(1<< 27);}' unless defined(&TVDAC_STATE_CHG_EN);
    eval 'sub TVDAC_A_SENSE_CTL () {(1<< 26);}' unless defined(&TVDAC_A_SENSE_CTL);
    eval 'sub TVDAC_B_SENSE_CTL () {(1<< 25);}' unless defined(&TVDAC_B_SENSE_CTL);
    eval 'sub TVDAC_C_SENSE_CTL () {(1<< 24);}' unless defined(&TVDAC_C_SENSE_CTL);
    eval 'sub DAC_CTL_OVERRIDE () {(1<< 7);}' unless defined(&DAC_CTL_OVERRIDE);
    eval 'sub ENC_TVDAC_SLEW_FAST () {(1<< 6);}' unless defined(&ENC_TVDAC_SLEW_FAST);
    eval 'sub DAC_A_1_3_V () {(0<< 4);}' unless defined(&DAC_A_1_3_V);
    eval 'sub DAC_A_1_1_V () {(1<< 4);}' unless defined(&DAC_A_1_1_V);
    eval 'sub DAC_A_0_7_V () {(2<< 4);}' unless defined(&DAC_A_0_7_V);
    eval 'sub DAC_A_OFF () {(3<< 4);}' unless defined(&DAC_A_OFF);
    eval 'sub DAC_B_1_3_V () {(0<< 2);}' unless defined(&DAC_B_1_3_V);
    eval 'sub DAC_B_1_1_V () {(1<< 2);}' unless defined(&DAC_B_1_1_V);
    eval 'sub DAC_B_0_7_V () {(2<< 2);}' unless defined(&DAC_B_0_7_V);
    eval 'sub DAC_B_OFF () {(3<< 2);}' unless defined(&DAC_B_OFF);
    eval 'sub DAC_C_1_3_V () {(0<< 0);}' unless defined(&DAC_C_1_3_V);
    eval 'sub DAC_C_1_1_V () {(1<< 0);}' unless defined(&DAC_C_1_1_V);
    eval 'sub DAC_C_0_7_V () {(2<< 0);}' unless defined(&DAC_C_0_7_V);
    eval 'sub DAC_C_OFF () {(3<< 0);}' unless defined(&DAC_C_OFF);
    eval 'sub TV_CSC_Y () {0x68010;}' unless defined(&TV_CSC_Y);
    eval 'sub TV_RY_MASK () {0x7ff0000;}' unless defined(&TV_RY_MASK);
    eval 'sub TV_RY_SHIFT () {16;}' unless defined(&TV_RY_SHIFT);
    eval 'sub TV_GY_MASK () {0xfff;}' unless defined(&TV_GY_MASK);
    eval 'sub TV_GY_SHIFT () {0;}' unless defined(&TV_GY_SHIFT);
    eval 'sub TV_CSC_Y2 () {0x68014;}' unless defined(&TV_CSC_Y2);
    eval 'sub TV_BY_MASK () {0x7ff0000;}' unless defined(&TV_BY_MASK);
    eval 'sub TV_BY_SHIFT () {16;}' unless defined(&TV_BY_SHIFT);
    eval 'sub TV_AY_MASK () {0x3ff;}' unless defined(&TV_AY_MASK);
    eval 'sub TV_AY_SHIFT () {0;}' unless defined(&TV_AY_SHIFT);
    eval 'sub TV_CSC_U () {0x68018;}' unless defined(&TV_CSC_U);
    eval 'sub TV_RU_MASK () {0x7ff0000;}' unless defined(&TV_RU_MASK);
    eval 'sub TV_RU_SHIFT () {16;}' unless defined(&TV_RU_SHIFT);
    eval 'sub TV_GU_MASK () {0x7ff;}' unless defined(&TV_GU_MASK);
    eval 'sub TV_GU_SHIFT () {0;}' unless defined(&TV_GU_SHIFT);
    eval 'sub TV_CSC_U2 () {0x6801c;}' unless defined(&TV_CSC_U2);
    eval 'sub TV_BU_MASK () {0x7ff0000;}' unless defined(&TV_BU_MASK);
    eval 'sub TV_BU_SHIFT () {16;}' unless defined(&TV_BU_SHIFT);
    eval 'sub TV_AU_MASK () {0x3ff;}' unless defined(&TV_AU_MASK);
    eval 'sub TV_AU_SHIFT () {0;}' unless defined(&TV_AU_SHIFT);
    eval 'sub TV_CSC_V () {0x68020;}' unless defined(&TV_CSC_V);
    eval 'sub TV_RV_MASK () {0xfff0000;}' unless defined(&TV_RV_MASK);
    eval 'sub TV_RV_SHIFT () {16;}' unless defined(&TV_RV_SHIFT);
    eval 'sub TV_GV_MASK () {0x7ff;}' unless defined(&TV_GV_MASK);
    eval 'sub TV_GV_SHIFT () {0;}' unless defined(&TV_GV_SHIFT);
    eval 'sub TV_CSC_V2 () {0x68024;}' unless defined(&TV_CSC_V2);
    eval 'sub TV_BV_MASK () {0x7ff0000;}' unless defined(&TV_BV_MASK);
    eval 'sub TV_BV_SHIFT () {16;}' unless defined(&TV_BV_SHIFT);
    eval 'sub TV_AV_MASK () {0x7ff;}' unless defined(&TV_AV_MASK);
    eval 'sub TV_AV_SHIFT () {0;}' unless defined(&TV_AV_SHIFT);
    eval 'sub TV_CLR_KNOBS () {0x68028;}' unless defined(&TV_CLR_KNOBS);
    eval 'sub TV_BRIGHTNESS_MASK () {0xff000000;}' unless defined(&TV_BRIGHTNESS_MASK);
    eval 'sub TV_BRIGHTNESS_SHIFT () {24;}' unless defined(&TV_BRIGHTNESS_SHIFT);
    eval 'sub TV_CONTRAST_MASK () {0xff0000;}' unless defined(&TV_CONTRAST_MASK);
    eval 'sub TV_CONTRAST_SHIFT () {16;}' unless defined(&TV_CONTRAST_SHIFT);
    eval 'sub TV_SATURATION_MASK () {0xff00;}' unless defined(&TV_SATURATION_MASK);
    eval 'sub TV_SATURATION_SHIFT () {8;}' unless defined(&TV_SATURATION_SHIFT);
    eval 'sub TV_HUE_MASK () {0xff;}' unless defined(&TV_HUE_MASK);
    eval 'sub TV_HUE_SHIFT () {0;}' unless defined(&TV_HUE_SHIFT);
    eval 'sub TV_CLR_LEVEL () {0x6802c;}' unless defined(&TV_CLR_LEVEL);
    eval 'sub TV_BLACK_LEVEL_MASK () {0x1ff0000;}' unless defined(&TV_BLACK_LEVEL_MASK);
    eval 'sub TV_BLACK_LEVEL_SHIFT () {16;}' unless defined(&TV_BLACK_LEVEL_SHIFT);
    eval 'sub TV_BLANK_LEVEL_MASK () {0x1ff;}' unless defined(&TV_BLANK_LEVEL_MASK);
    eval 'sub TV_BLANK_LEVEL_SHIFT () {0;}' unless defined(&TV_BLANK_LEVEL_SHIFT);
    eval 'sub TV_H_CTL_1 () {0x68030;}' unless defined(&TV_H_CTL_1);
    eval 'sub TV_HSYNC_END_MASK () {0x1fff0000;}' unless defined(&TV_HSYNC_END_MASK);
    eval 'sub TV_HSYNC_END_SHIFT () {16;}' unless defined(&TV_HSYNC_END_SHIFT);
    eval 'sub TV_HTOTAL_MASK () {0x1fff;}' unless defined(&TV_HTOTAL_MASK);
    eval 'sub TV_HTOTAL_SHIFT () {0;}' unless defined(&TV_HTOTAL_SHIFT);
    eval 'sub TV_H_CTL_2 () {0x68034;}' unless defined(&TV_H_CTL_2);
    eval 'sub TV_BURST_ENA () {(1<< 31);}' unless defined(&TV_BURST_ENA);
    eval 'sub TV_HBURST_START_SHIFT () {16;}' unless defined(&TV_HBURST_START_SHIFT);
    eval 'sub TV_HBURST_START_MASK () {0x1fff0000;}' unless defined(&TV_HBURST_START_MASK);
    eval 'sub TV_HBURST_LEN_SHIFT () {0;}' unless defined(&TV_HBURST_LEN_SHIFT);
    eval 'sub TV_HBURST_LEN_MASK () {0x1fff;}' unless defined(&TV_HBURST_LEN_MASK);
    eval 'sub TV_H_CTL_3 () {0x68038;}' unless defined(&TV_H_CTL_3);
    eval 'sub TV_HBLANK_END_SHIFT () {16;}' unless defined(&TV_HBLANK_END_SHIFT);
    eval 'sub TV_HBLANK_END_MASK () {0x1fff0000;}' unless defined(&TV_HBLANK_END_MASK);
    eval 'sub TV_HBLANK_START_SHIFT () {0;}' unless defined(&TV_HBLANK_START_SHIFT);
    eval 'sub TV_HBLANK_START_MASK () {0x1fff;}' unless defined(&TV_HBLANK_START_MASK);
    eval 'sub TV_V_CTL_1 () {0x6803c;}' unless defined(&TV_V_CTL_1);
    eval 'sub TV_NBR_END_SHIFT () {16;}' unless defined(&TV_NBR_END_SHIFT);
    eval 'sub TV_NBR_END_MASK () {0x7ff0000;}' unless defined(&TV_NBR_END_MASK);
    eval 'sub TV_VI_END_F1_SHIFT () {8;}' unless defined(&TV_VI_END_F1_SHIFT);
    eval 'sub TV_VI_END_F1_MASK () {0x3f00;}' unless defined(&TV_VI_END_F1_MASK);
    eval 'sub TV_VI_END_F2_SHIFT () {0;}' unless defined(&TV_VI_END_F2_SHIFT);
    eval 'sub TV_VI_END_F2_MASK () {0x3f;}' unless defined(&TV_VI_END_F2_MASK);
    eval 'sub TV_V_CTL_2 () {0x68040;}' unless defined(&TV_V_CTL_2);
    eval 'sub TV_VSYNC_LEN_MASK () {0x7ff0000;}' unless defined(&TV_VSYNC_LEN_MASK);
    eval 'sub TV_VSYNC_LEN_SHIFT () {16;}' unless defined(&TV_VSYNC_LEN_SHIFT);
    eval 'sub TV_VSYNC_START_F1_MASK () {0x7f00;}' unless defined(&TV_VSYNC_START_F1_MASK);
    eval 'sub TV_VSYNC_START_F1_SHIFT () {8;}' unless defined(&TV_VSYNC_START_F1_SHIFT);
    eval 'sub TV_VSYNC_START_F2_MASK () {0x7f;}' unless defined(&TV_VSYNC_START_F2_MASK);
    eval 'sub TV_VSYNC_START_F2_SHIFT () {0;}' unless defined(&TV_VSYNC_START_F2_SHIFT);
    eval 'sub TV_V_CTL_3 () {0x68044;}' unless defined(&TV_V_CTL_3);
    eval 'sub TV_EQUAL_ENA () {(1<< 31);}' unless defined(&TV_EQUAL_ENA);
    eval 'sub TV_VEQ_LEN_MASK () {0x7f0000;}' unless defined(&TV_VEQ_LEN_MASK);
    eval 'sub TV_VEQ_LEN_SHIFT () {16;}' unless defined(&TV_VEQ_LEN_SHIFT);
    eval 'sub TV_VEQ_START_F1_MASK () {0x7f00;}' unless defined(&TV_VEQ_START_F1_MASK);
    eval 'sub TV_VEQ_START_F1_SHIFT () {8;}' unless defined(&TV_VEQ_START_F1_SHIFT);
    eval 'sub TV_VEQ_START_F2_MASK () {0x7f;}' unless defined(&TV_VEQ_START_F2_MASK);
    eval 'sub TV_VEQ_START_F2_SHIFT () {0;}' unless defined(&TV_VEQ_START_F2_SHIFT);
    eval 'sub TV_V_CTL_4 () {0x68048;}' unless defined(&TV_V_CTL_4);
    eval 'sub TV_VBURST_START_F1_MASK () {0x3f0000;}' unless defined(&TV_VBURST_START_F1_MASK);
    eval 'sub TV_VBURST_START_F1_SHIFT () {16;}' unless defined(&TV_VBURST_START_F1_SHIFT);
    eval 'sub TV_VBURST_END_F1_MASK () {0xff;}' unless defined(&TV_VBURST_END_F1_MASK);
    eval 'sub TV_VBURST_END_F1_SHIFT () {0;}' unless defined(&TV_VBURST_END_F1_SHIFT);
    eval 'sub TV_V_CTL_5 () {0x6804c;}' unless defined(&TV_V_CTL_5);
    eval 'sub TV_VBURST_START_F2_MASK () {0x3f0000;}' unless defined(&TV_VBURST_START_F2_MASK);
    eval 'sub TV_VBURST_START_F2_SHIFT () {16;}' unless defined(&TV_VBURST_START_F2_SHIFT);
    eval 'sub TV_VBURST_END_F2_MASK () {0xff;}' unless defined(&TV_VBURST_END_F2_MASK);
    eval 'sub TV_VBURST_END_F2_SHIFT () {0;}' unless defined(&TV_VBURST_END_F2_SHIFT);
    eval 'sub TV_V_CTL_6 () {0x68050;}' unless defined(&TV_V_CTL_6);
    eval 'sub TV_VBURST_START_F3_MASK () {0x3f0000;}' unless defined(&TV_VBURST_START_F3_MASK);
    eval 'sub TV_VBURST_START_F3_SHIFT () {16;}' unless defined(&TV_VBURST_START_F3_SHIFT);
    eval 'sub TV_VBURST_END_F3_MASK () {0xff;}' unless defined(&TV_VBURST_END_F3_MASK);
    eval 'sub TV_VBURST_END_F3_SHIFT () {0;}' unless defined(&TV_VBURST_END_F3_SHIFT);
    eval 'sub TV_V_CTL_7 () {0x68054;}' unless defined(&TV_V_CTL_7);
    eval 'sub TV_VBURST_START_F4_MASK () {0x3f0000;}' unless defined(&TV_VBURST_START_F4_MASK);
    eval 'sub TV_VBURST_START_F4_SHIFT () {16;}' unless defined(&TV_VBURST_START_F4_SHIFT);
    eval 'sub TV_VBURST_END_F4_MASK () {0xff;}' unless defined(&TV_VBURST_END_F4_MASK);
    eval 'sub TV_VBURST_END_F4_SHIFT () {0;}' unless defined(&TV_VBURST_END_F4_SHIFT);
    eval 'sub TV_SC_CTL_1 () {0x68060;}' unless defined(&TV_SC_CTL_1);
    eval 'sub TV_SC_DDA1_EN () {(1<< 31);}' unless defined(&TV_SC_DDA1_EN);
    eval 'sub TV_SC_DDA2_EN () {(1<< 30);}' unless defined(&TV_SC_DDA2_EN);
    eval 'sub TV_SC_DDA3_EN () {(1<< 29);}' unless defined(&TV_SC_DDA3_EN);
    eval 'sub TV_SC_RESET_EVERY_2 () {(0<< 24);}' unless defined(&TV_SC_RESET_EVERY_2);
    eval 'sub TV_SC_RESET_EVERY_4 () {(1<< 24);}' unless defined(&TV_SC_RESET_EVERY_4);
    eval 'sub TV_SC_RESET_EVERY_8 () {(2<< 24);}' unless defined(&TV_SC_RESET_EVERY_8);
    eval 'sub TV_SC_RESET_NEVER () {(3<< 24);}' unless defined(&TV_SC_RESET_NEVER);
    eval 'sub TV_BURST_LEVEL_MASK () {0xff0000;}' unless defined(&TV_BURST_LEVEL_MASK);
    eval 'sub TV_BURST_LEVEL_SHIFT () {16;}' unless defined(&TV_BURST_LEVEL_SHIFT);
    eval 'sub TV_SCDDA1_INC_MASK () {0xfff;}' unless defined(&TV_SCDDA1_INC_MASK);
    eval 'sub TV_SCDDA1_INC_SHIFT () {0;}' unless defined(&TV_SCDDA1_INC_SHIFT);
    eval 'sub TV_SC_CTL_2 () {0x68064;}' unless defined(&TV_SC_CTL_2);
    eval 'sub TV_SCDDA2_SIZE_MASK () {0x7fff0000;}' unless defined(&TV_SCDDA2_SIZE_MASK);
    eval 'sub TV_SCDDA2_SIZE_SHIFT () {16;}' unless defined(&TV_SCDDA2_SIZE_SHIFT);
    eval 'sub TV_SCDDA2_INC_MASK () {0x7fff;}' unless defined(&TV_SCDDA2_INC_MASK);
    eval 'sub TV_SCDDA2_INC_SHIFT () {0;}' unless defined(&TV_SCDDA2_INC_SHIFT);
    eval 'sub TV_SC_CTL_3 () {0x68068;}' unless defined(&TV_SC_CTL_3);
    eval 'sub TV_SCDDA3_SIZE_MASK () {0x7fff0000;}' unless defined(&TV_SCDDA3_SIZE_MASK);
    eval 'sub TV_SCDDA3_SIZE_SHIFT () {16;}' unless defined(&TV_SCDDA3_SIZE_SHIFT);
    eval 'sub TV_SCDDA3_INC_MASK () {0x7fff;}' unless defined(&TV_SCDDA3_INC_MASK);
    eval 'sub TV_SCDDA3_INC_SHIFT () {0;}' unless defined(&TV_SCDDA3_INC_SHIFT);
    eval 'sub TV_WIN_POS () {0x68070;}' unless defined(&TV_WIN_POS);
    eval 'sub TV_XPOS_MASK () {0x1fff0000;}' unless defined(&TV_XPOS_MASK);
    eval 'sub TV_XPOS_SHIFT () {16;}' unless defined(&TV_XPOS_SHIFT);
    eval 'sub TV_YPOS_MASK () {0xfff;}' unless defined(&TV_YPOS_MASK);
    eval 'sub TV_YPOS_SHIFT () {0;}' unless defined(&TV_YPOS_SHIFT);
    eval 'sub TV_WIN_SIZE () {0x68074;}' unless defined(&TV_WIN_SIZE);
    eval 'sub TV_XSIZE_MASK () {0x1fff0000;}' unless defined(&TV_XSIZE_MASK);
    eval 'sub TV_XSIZE_SHIFT () {16;}' unless defined(&TV_XSIZE_SHIFT);
    eval 'sub TV_YSIZE_MASK () {0xfff;}' unless defined(&TV_YSIZE_MASK);
    eval 'sub TV_YSIZE_SHIFT () {0;}' unless defined(&TV_YSIZE_SHIFT);
    eval 'sub TV_FILTER_CTL_1 () {0x68080;}' unless defined(&TV_FILTER_CTL_1);
    eval 'sub TV_AUTO_SCALE () {(1<< 31);}' unless defined(&TV_AUTO_SCALE);
    eval 'sub TV_V_FILTER_BYPASS () {(1<< 29);}' unless defined(&TV_V_FILTER_BYPASS);
    eval 'sub TV_VADAPT () {(1<< 28);}' unless defined(&TV_VADAPT);
    eval 'sub TV_VADAPT_MODE_MASK () {(3<< 26);}' unless defined(&TV_VADAPT_MODE_MASK);
    eval 'sub TV_VADAPT_MODE_LEAST () {(0<< 26);}' unless defined(&TV_VADAPT_MODE_LEAST);
    eval 'sub TV_VADAPT_MODE_MODERATE () {(1<< 26);}' unless defined(&TV_VADAPT_MODE_MODERATE);
    eval 'sub TV_VADAPT_MODE_MOST () {(3<< 26);}' unless defined(&TV_VADAPT_MODE_MOST);
    eval 'sub TV_HSCALE_FRAC_MASK () {0x3fff;}' unless defined(&TV_HSCALE_FRAC_MASK);
    eval 'sub TV_HSCALE_FRAC_SHIFT () {0;}' unless defined(&TV_HSCALE_FRAC_SHIFT);
    eval 'sub TV_FILTER_CTL_2 () {0x68084;}' unless defined(&TV_FILTER_CTL_2);
    eval 'sub TV_VSCALE_INT_MASK () {0x38000;}' unless defined(&TV_VSCALE_INT_MASK);
    eval 'sub TV_VSCALE_INT_SHIFT () {15;}' unless defined(&TV_VSCALE_INT_SHIFT);
    eval 'sub TV_VSCALE_FRAC_MASK () {0x7fff;}' unless defined(&TV_VSCALE_FRAC_MASK);
    eval 'sub TV_VSCALE_FRAC_SHIFT () {0;}' unless defined(&TV_VSCALE_FRAC_SHIFT);
    eval 'sub TV_FILTER_CTL_3 () {0x68088;}' unless defined(&TV_FILTER_CTL_3);
    eval 'sub TV_VSCALE_IP_INT_MASK () {0x38000;}' unless defined(&TV_VSCALE_IP_INT_MASK);
    eval 'sub TV_VSCALE_IP_INT_SHIFT () {15;}' unless defined(&TV_VSCALE_IP_INT_SHIFT);
    eval 'sub TV_VSCALE_IP_FRAC_MASK () {0x7fff;}' unless defined(&TV_VSCALE_IP_FRAC_MASK);
    eval 'sub TV_VSCALE_IP_FRAC_SHIFT () {0;}' unless defined(&TV_VSCALE_IP_FRAC_SHIFT);
    eval 'sub TV_CC_CONTROL () {0x68090;}' unless defined(&TV_CC_CONTROL);
    eval 'sub TV_CC_ENABLE () {(1<< 31);}' unless defined(&TV_CC_ENABLE);
    eval 'sub TV_CC_FID_MASK () {(1<< 27);}' unless defined(&TV_CC_FID_MASK);
    eval 'sub TV_CC_FID_SHIFT () {27;}' unless defined(&TV_CC_FID_SHIFT);
    eval 'sub TV_CC_HOFF_MASK () {0x3ff0000;}' unless defined(&TV_CC_HOFF_MASK);
    eval 'sub TV_CC_HOFF_SHIFT () {16;}' unless defined(&TV_CC_HOFF_SHIFT);
    eval 'sub TV_CC_LINE_MASK () {0x3f;}' unless defined(&TV_CC_LINE_MASK);
    eval 'sub TV_CC_LINE_SHIFT () {0;}' unless defined(&TV_CC_LINE_SHIFT);
    eval 'sub TV_CC_DATA () {0x68094;}' unless defined(&TV_CC_DATA);
    eval 'sub TV_CC_RDY () {(1<< 31);}' unless defined(&TV_CC_RDY);
    eval 'sub TV_CC_DATA_2_MASK () {0x7f0000;}' unless defined(&TV_CC_DATA_2_MASK);
    eval 'sub TV_CC_DATA_2_SHIFT () {16;}' unless defined(&TV_CC_DATA_2_SHIFT);
    eval 'sub TV_CC_DATA_1_MASK () {0x7f;}' unless defined(&TV_CC_DATA_1_MASK);
    eval 'sub TV_CC_DATA_1_SHIFT () {0;}' unless defined(&TV_CC_DATA_1_SHIFT);
    eval 'sub TV_H_LUMA_0 () {0x68100;}' unless defined(&TV_H_LUMA_0);
    eval 'sub TV_H_LUMA_59 () {0x681ec;}' unless defined(&TV_H_LUMA_59);
    eval 'sub TV_H_CHROMA_0 () {0x68200;}' unless defined(&TV_H_CHROMA_0);
    eval 'sub TV_H_CHROMA_59 () {0x682ec;}' unless defined(&TV_H_CHROMA_59);
    eval 'sub TV_V_LUMA_0 () {0x68300;}' unless defined(&TV_V_LUMA_0);
    eval 'sub TV_V_LUMA_42 () {0x683a8;}' unless defined(&TV_V_LUMA_42);
    eval 'sub TV_V_CHROMA_0 () {0x68400;}' unless defined(&TV_V_CHROMA_0);
    eval 'sub TV_V_CHROMA_42 () {0x684a8;}' unless defined(&TV_V_CHROMA_42);
    eval 'sub PIPEADSL () {0x70000;}' unless defined(&PIPEADSL);
    eval 'sub PIPEACONF () {0x70008;}' unless defined(&PIPEACONF);
    eval 'sub PIPEACONF_ENABLE () {(1<<31);}' unless defined(&PIPEACONF_ENABLE);
    eval 'sub PIPEACONF_DISABLE () {0;}' unless defined(&PIPEACONF_DISABLE);
    eval 'sub PIPEACONF_DOUBLE_WIDE () {(1<<30);}' unless defined(&PIPEACONF_DOUBLE_WIDE);
    eval 'sub I965_PIPECONF_ACTIVE () {(1<<30);}' unless defined(&I965_PIPECONF_ACTIVE);
    eval 'sub PIPEACONF_SINGLE_WIDE () {0;}' unless defined(&PIPEACONF_SINGLE_WIDE);
    eval 'sub PIPEACONF_PIPE_UNLOCKED () {0;}' unless defined(&PIPEACONF_PIPE_UNLOCKED);
    eval 'sub PIPEACONF_PIPE_LOCKED () {(1<<25);}' unless defined(&PIPEACONF_PIPE_LOCKED);
    eval 'sub PIPEACONF_PALETTE () {0;}' unless defined(&PIPEACONF_PALETTE);
    eval 'sub PIPEACONF_GAMMA () {(1<<24);}' unless defined(&PIPEACONF_GAMMA);
    eval 'sub PIPECONF_FORCE_BORDER () {(1<<25);}' unless defined(&PIPECONF_FORCE_BORDER);
    eval 'sub PIPECONF_PROGRESSIVE () {(0<< 21);}' unless defined(&PIPECONF_PROGRESSIVE);
    eval 'sub PIPECONF_INTERLACE_W_FIELD_INDICATION () {(6<< 21);}' unless defined(&PIPECONF_INTERLACE_W_FIELD_INDICATION);
    eval 'sub PIPECONF_INTERLACE_FIELD_0_ONLY () {(7<< 21);}' unless defined(&PIPECONF_INTERLACE_FIELD_0_ONLY);
    eval 'sub PIPEASTAT () {0x70024;}' unless defined(&PIPEASTAT);
    eval 'sub PIPE_FIFO_UNDERRUN_STATUS () {(1<<31);}' unless defined(&PIPE_FIFO_UNDERRUN_STATUS);
    eval 'sub PIPE_CRC_ERROR_ENABLE () {(1<<29);}' unless defined(&PIPE_CRC_ERROR_ENABLE);
    eval 'sub PIPE_CRC_DONE_ENABLE () {(1<<28);}' unless defined(&PIPE_CRC_DONE_ENABLE);
    eval 'sub PIPE_GMBUS_EVENT_ENABLE () {(1<<27);}' unless defined(&PIPE_GMBUS_EVENT_ENABLE);
    eval 'sub PIPE_HOTPLUG_INTERRUPT_ENABLE () {(1<<26);}' unless defined(&PIPE_HOTPLUG_INTERRUPT_ENABLE);
    eval 'sub PIPE_VSYNC_INTERRUPT_ENABLE () {(1<<25);}' unless defined(&PIPE_VSYNC_INTERRUPT_ENABLE);
    eval 'sub PIPE_DISPLAY_LINE_COMPARE_ENABLE () {(1<<24);}' unless defined(&PIPE_DISPLAY_LINE_COMPARE_ENABLE);
    eval 'sub PIPE_DPST_EVENT_ENABLE () {(1<<23);}' unless defined(&PIPE_DPST_EVENT_ENABLE);
    eval 'sub PIPE_LEGACY_BLC_EVENT_ENABLE () {(1<<22);}' unless defined(&PIPE_LEGACY_BLC_EVENT_ENABLE);
    eval 'sub PIPE_ODD_FIELD_INTERRUPT_ENABLE () {(1<<21);}' unless defined(&PIPE_ODD_FIELD_INTERRUPT_ENABLE);
    eval 'sub PIPE_EVEN_FIELD_INTERRUPT_ENABLE () {(1<<20);}' unless defined(&PIPE_EVEN_FIELD_INTERRUPT_ENABLE);
    eval 'sub PIPE_HOTPLUG_TV_INTERRUPT_ENABLE () {(1<<18);}' unless defined(&PIPE_HOTPLUG_TV_INTERRUPT_ENABLE);
    eval 'sub PIPE_START_VBLANK_INTERRUPT_ENABLE () {(1<<18);}' unless defined(&PIPE_START_VBLANK_INTERRUPT_ENABLE);
    eval 'sub PIPE_VBLANK_INTERRUPT_ENABLE () {(1<<17);}' unless defined(&PIPE_VBLANK_INTERRUPT_ENABLE);
    eval 'sub PIPE_OVERLAY_UPDATED_ENABLE () {(1<<16);}' unless defined(&PIPE_OVERLAY_UPDATED_ENABLE);
    eval 'sub PIPE_CRC_ERROR_INTERRUPT_STATUS () {(1<<13);}' unless defined(&PIPE_CRC_ERROR_INTERRUPT_STATUS);
    eval 'sub PIPE_CRC_DONE_INTERRUPT_STATUS () {(1<<12);}' unless defined(&PIPE_CRC_DONE_INTERRUPT_STATUS);
    eval 'sub PIPE_GMBUS_INTERRUPT_STATUS () {(1<<11);}' unless defined(&PIPE_GMBUS_INTERRUPT_STATUS);
    eval 'sub PIPE_HOTPLUG_INTERRUPT_STATUS () {(1<<10);}' unless defined(&PIPE_HOTPLUG_INTERRUPT_STATUS);
    eval 'sub PIPE_VSYNC_INTERRUPT_STATUS () {(1<<9);}' unless defined(&PIPE_VSYNC_INTERRUPT_STATUS);
    eval 'sub PIPE_DISPLAY_LINE_COMPARE_STATUS () {(1<<8);}' unless defined(&PIPE_DISPLAY_LINE_COMPARE_STATUS);
    eval 'sub PIPE_DPST_EVENT_STATUS () {(1<<7);}' unless defined(&PIPE_DPST_EVENT_STATUS);
    eval 'sub PIPE_LEGACY_BLC_EVENT_STATUS () {(1<<6);}' unless defined(&PIPE_LEGACY_BLC_EVENT_STATUS);
    eval 'sub PIPE_ODD_FIELD_INTERRUPT_STATUS () {(1<<5);}' unless defined(&PIPE_ODD_FIELD_INTERRUPT_STATUS);
    eval 'sub PIPE_EVEN_FIELD_INTERRUPT_STATUS () {(1<<4);}' unless defined(&PIPE_EVEN_FIELD_INTERRUPT_STATUS);
    eval 'sub PIPE_HOTPLUG_TV_INTERRUPT_STATUS () {(1<<2);}' unless defined(&PIPE_HOTPLUG_TV_INTERRUPT_STATUS);
    eval 'sub PIPE_START_VBLANK_INTERRUPT_STATUS () {(1<<2);}' unless defined(&PIPE_START_VBLANK_INTERRUPT_STATUS);
    eval 'sub PIPE_VBLANK_INTERRUPT_STATUS () {(1<<1);}' unless defined(&PIPE_VBLANK_INTERRUPT_STATUS);
    eval 'sub PIPE_OVERLAY_UPDATED_STATUS () {(1<<0);}' unless defined(&PIPE_OVERLAY_UPDATED_STATUS);
    eval 'sub DSPARB () {0x70030;}' unless defined(&DSPARB);
    eval 'sub DSPARB_CSTART_MASK () {(0x7f << 7);}' unless defined(&DSPARB_CSTART_MASK);
    eval 'sub DSPARB_CSTART_SHIFT () {7;}' unless defined(&DSPARB_CSTART_SHIFT);
    eval 'sub DSPARB_BSTART_MASK () {(0x7f);}' unless defined(&DSPARB_BSTART_MASK);
    eval 'sub DSPARB_BSTART_SHIFT () {0;}' unless defined(&DSPARB_BSTART_SHIFT);
    eval 'sub PIPEAFRAMEHIGH () {0x70040;}' unless defined(&PIPEAFRAMEHIGH);
    eval 'sub PIPE_FRAME_HIGH_MASK () {0xffff;}' unless defined(&PIPE_FRAME_HIGH_MASK);
    eval 'sub PIPE_FRAME_HIGH_SHIFT () {0;}' unless defined(&PIPE_FRAME_HIGH_SHIFT);
    eval 'sub PIPEAFRAMEPIXEL () {0x70044;}' unless defined(&PIPEAFRAMEPIXEL);
    eval 'sub PIPE_FRAME_LOW_MASK () {0xff000000;}' unless defined(&PIPE_FRAME_LOW_MASK);
    eval 'sub PIPE_FRAME_LOW_SHIFT () {24;}' unless defined(&PIPE_FRAME_LOW_SHIFT);
    eval 'sub PIPE_PIXEL_MASK () {0xffffff;}' unless defined(&PIPE_PIXEL_MASK);
    eval 'sub PIPE_PIXEL_SHIFT () {0;}' unless defined(&PIPE_PIXEL_SHIFT);
    eval 'sub CURACNTR () {0x70080;}' unless defined(&CURACNTR);
    eval 'sub CURSOR_MODE_DISABLE () {0x;}' unless defined(&CURSOR_MODE_DISABLE);
    eval 'sub CURSOR_MODE_64_32B_AX () {0x7;}' unless defined(&CURSOR_MODE_64_32B_AX);
    eval 'sub CURSOR_MODE_64_ARGB_AX () {((1<< 5) |  &CURSOR_MODE_64_32B_AX);}' unless defined(&CURSOR_MODE_64_ARGB_AX);
    eval 'sub MCURSOR_GAMMA_ENABLE () {(1<< 26);}' unless defined(&MCURSOR_GAMMA_ENABLE);
    eval 'sub CURABASE () {0x70084;}' unless defined(&CURABASE);
    eval 'sub CURAPOS () {0x70088;}' unless defined(&CURAPOS);
    eval 'sub CURSOR_POS_MASK () {0x7ff;}' unless defined(&CURSOR_POS_MASK);
    eval 'sub CURSOR_POS_SIGN () {0x8000;}' unless defined(&CURSOR_POS_SIGN);
    eval 'sub CURSOR_X_SHIFT () {0;}' unless defined(&CURSOR_X_SHIFT);
    eval 'sub CURSOR_Y_SHIFT () {16;}' unless defined(&CURSOR_Y_SHIFT);
    eval 'sub CURBCNTR () {0x700c0;}' unless defined(&CURBCNTR);
    eval 'sub CURBBASE () {0x700c4;}' unless defined(&CURBBASE);
    eval 'sub CURBPOS () {0x700c8;}' unless defined(&CURBPOS);
    eval 'sub DSPACNTR () {0x70180;}' unless defined(&DSPACNTR);
    eval 'sub DISPLAY_PLANE_ENABLE () {(1<<31);}' unless defined(&DISPLAY_PLANE_ENABLE);
    eval 'sub DISPLAY_PLANE_DISABLE () {0;}' unless defined(&DISPLAY_PLANE_DISABLE);
    eval 'sub DISPPLANE_GAMMA_ENABLE () {(1<<30);}' unless defined(&DISPPLANE_GAMMA_ENABLE);
    eval 'sub DISPPLANE_GAMMA_DISABLE () {0;}' unless defined(&DISPPLANE_GAMMA_DISABLE);
    eval 'sub DISPPLANE_PIXFORMAT_MASK () {(0xf<<26);}' unless defined(&DISPPLANE_PIXFORMAT_MASK);
    eval 'sub DISPPLANE_8BPP () {(0x2<<26);}' unless defined(&DISPPLANE_8BPP);
    eval 'sub DISPPLANE_15_16BPP () {(0x4<<26);}' unless defined(&DISPPLANE_15_16BPP);
    eval 'sub DISPPLANE_16BPP () {(0x5<<26);}' unless defined(&DISPPLANE_16BPP);
    eval 'sub DISPPLANE_32BPP_NO_ALPHA () {(0x6<<26);}' unless defined(&DISPPLANE_32BPP_NO_ALPHA);
    eval 'sub DISPPLANE_32BPP () {(0x7<<26);}' unless defined(&DISPPLANE_32BPP);
    eval 'sub DISPPLANE_STEREO_ENABLE () {(1<<25);}' unless defined(&DISPPLANE_STEREO_ENABLE);
    eval 'sub DISPPLANE_STEREO_DISABLE () {0;}' unless defined(&DISPPLANE_STEREO_DISABLE);
    eval 'sub DISPPLANE_SEL_PIPE_MASK () {(1<<24);}' unless defined(&DISPPLANE_SEL_PIPE_MASK);
    eval 'sub DISPPLANE_SEL_PIPE_A () {0;}' unless defined(&DISPPLANE_SEL_PIPE_A);
    eval 'sub DISPPLANE_SEL_PIPE_B () {(1<<24);}' unless defined(&DISPPLANE_SEL_PIPE_B);
    eval 'sub DISPPLANE_SRC_KEY_ENABLE () {(1<<22);}' unless defined(&DISPPLANE_SRC_KEY_ENABLE);
    eval 'sub DISPPLANE_SRC_KEY_DISABLE () {0;}' unless defined(&DISPPLANE_SRC_KEY_DISABLE);
    eval 'sub DISPPLANE_LINE_DOUBLE () {(1<<20);}' unless defined(&DISPPLANE_LINE_DOUBLE);
    eval 'sub DISPPLANE_NO_LINE_DOUBLE () {0;}' unless defined(&DISPPLANE_NO_LINE_DOUBLE);
    eval 'sub DISPPLANE_STEREO_POLARITY_FIRST () {0;}' unless defined(&DISPPLANE_STEREO_POLARITY_FIRST);
    eval 'sub DISPPLANE_STEREO_POLARITY_SECOND () {(1<<18);}' unless defined(&DISPPLANE_STEREO_POLARITY_SECOND);
    eval 'sub DSPAADDR () {0x70184;}' unless defined(&DSPAADDR);
    eval 'sub DSPASTRIDE () {0x70188;}' unless defined(&DSPASTRIDE);
    eval 'sub DSPAPOS () {0x7018c;}' unless defined(&DSPAPOS);
    eval 'sub DSPASIZE () {0x70190;}' unless defined(&DSPASIZE);
    eval 'sub DSPASURF () {0x7019c;}' unless defined(&DSPASURF);
    eval 'sub DSPATILEOFF () {0x701a4;}' unless defined(&DSPATILEOFF);
    eval 'sub SWF00 () {0x71410;}' unless defined(&SWF00);
    eval 'sub SWF01 () {0x71414;}' unless defined(&SWF01);
    eval 'sub SWF02 () {0x71418;}' unless defined(&SWF02);
    eval 'sub SWF03 () {0x7141c;}' unless defined(&SWF03);
    eval 'sub SWF04 () {0x71420;}' unless defined(&SWF04);
    eval 'sub SWF05 () {0x71424;}' unless defined(&SWF05);
    eval 'sub SWF06 () {0x71428;}' unless defined(&SWF06);
    eval 'sub SWF10 () {0x70410;}' unless defined(&SWF10);
    eval 'sub SWF11 () {0x70414;}' unless defined(&SWF11);
    eval 'sub SWF14 () {0x71420;}' unless defined(&SWF14);
    eval 'sub SWF30 () {0x72414;}' unless defined(&SWF30);
    eval 'sub SWF31 () {0x72418;}' unless defined(&SWF31);
    eval 'sub SWF32 () {0x7241c;}' unless defined(&SWF32);
    eval 'sub PIPEBDSL () {0x71000;}' unless defined(&PIPEBDSL);
    eval 'sub PIPEBCONF () {0x71008;}' unless defined(&PIPEBCONF);
    eval 'sub PIPEBSTAT () {0x71024;}' unless defined(&PIPEBSTAT);
    eval 'sub PIPEBFRAMEHIGH () {0x71040;}' unless defined(&PIPEBFRAMEHIGH);
    eval 'sub PIPEBFRAMEPIXEL () {0x71044;}' unless defined(&PIPEBFRAMEPIXEL);
    eval 'sub DSPBCNTR () {0x71180;}' unless defined(&DSPBCNTR);
    eval 'sub DISPPLANE_ALPHA_TRANS_ENABLE () {(1<<15);}' unless defined(&DISPPLANE_ALPHA_TRANS_ENABLE);
    eval 'sub DISPPLANE_ALPHA_TRANS_DISABLE () {0;}' unless defined(&DISPPLANE_ALPHA_TRANS_DISABLE);
    eval 'sub DISPPLANE_SPRITE_ABOVE_DISPLAY () {0;}' unless defined(&DISPPLANE_SPRITE_ABOVE_DISPLAY);
    eval 'sub DISPPLANE_SPRITE_ABOVE_OVERLAY () {(1);}' unless defined(&DISPPLANE_SPRITE_ABOVE_OVERLAY);
    eval 'sub DSPBADDR () {0x71184;}' unless defined(&DSPBADDR);
    eval 'sub DSPBSTRIDE () {0x71188;}' unless defined(&DSPBSTRIDE);
    eval 'sub DSPBPOS () {0x7118c;}' unless defined(&DSPBPOS);
    eval 'sub DSPBSIZE () {0x71190;}' unless defined(&DSPBSIZE);
    eval 'sub DSPBSURF () {0x7119c;}' unless defined(&DSPBSURF);
    eval 'sub DSPBTILEOFF () {0x711a4;}' unless defined(&DSPBTILEOFF);
    eval 'sub VGACNTRL () {0x71400;}' unless defined(&VGACNTRL);
    eval 'sub VGA_DISP_DISABLE () {(1<< 31);}' unless defined(&VGA_DISP_DISABLE);
    eval 'sub VGA_2X_MODE () {(1<< 30);}' unless defined(&VGA_2X_MODE);
    eval 'sub VGA_PIPE_B_SELECT () {(1<< 29);}' unless defined(&VGA_PIPE_B_SELECT);
    eval 'sub IS_I830 {
        my($dev) = @_;
	    eval q((($dev)-> &pci_device == 0x3577));
    }' unless defined(&IS_I830);
    eval 'sub IS_845G {
        my($dev) = @_;
	    eval q((($dev)-> &pci_device == 0x2562));
    }' unless defined(&IS_845G);
    eval 'sub IS_I85X {
        my($dev) = @_;
	    eval q((($dev)-> &pci_device == 0x3582));
    }' unless defined(&IS_I85X);
    eval 'sub IS_I855 {
        my($dev) = @_;
	    eval q((($dev)-> &pci_device == 0x3582));
    }' unless defined(&IS_I855);
    eval 'sub IS_I865G {
        my($dev) = @_;
	    eval q((($dev)-> &pci_device == 0x2572));
    }' unless defined(&IS_I865G);
    eval 'sub IS_I915G {
        my($dev) = @_;
	    eval q((($dev)-> &pci_device == 0x2582 || ($dev)-> &pci_device == 0x258a));
    }' unless defined(&IS_I915G);
    eval 'sub IS_I915GM {
        my($dev) = @_;
	    eval q((($dev)-> &pci_device == 0x2592));
    }' unless defined(&IS_I915GM);
    eval 'sub IS_I945G {
        my($dev) = @_;
	    eval q((($dev)-> &pci_device == 0x2772));
    }' unless defined(&IS_I945G);
    eval 'sub IS_I945GM {
        my($dev) = @_;
	    eval q((($dev)-> &pci_device == 0x27a2 || ($dev)-> &pci_device == 0x27ae));
    }' unless defined(&IS_I945GM);
    eval 'sub IS_I965G {
        my($dev) = @_;
	    eval q((($dev)-> &pci_device == 0x2972 || ($dev)-> &pci_device == 0x2982 || ($dev)-> &pci_device == 0x2992 || ($dev)-> &pci_device == 0x29a2 || ($dev)-> &pci_device == 0x2a02 || ($dev)-> &pci_device == 0x2a12 || ($dev)-> &pci_device == 0x2a42 || ($dev)-> &pci_device == 0x2e02 || ($dev)-> &pci_device == 0x2e12 || ($dev)-> &pci_device == 0x2e22));
    }' unless defined(&IS_I965G);
    eval 'sub IS_I965GM {
        my($dev) = @_;
	    eval q((($dev)-> &pci_device == 0x2a02));
    }' unless defined(&IS_I965GM);
    eval 'sub IS_GM45 {
        my($dev) = @_;
	    eval q((($dev)-> &pci_device == 0x2a42));
    }' unless defined(&IS_GM45);
    eval 'sub IS_G4X {
        my($dev) = @_;
	    eval q((($dev)-> &pci_device == 0x2e02 || ($dev)-> &pci_device == 0x2e12 || ($dev)-> &pci_device == 0x2e22));
    }' unless defined(&IS_G4X);
    eval 'sub IS_G33 {
        my($dev) = @_;
	    eval q((($dev)-> &pci_device == 0x29c2 || ($dev)-> &pci_device == 0x29b2 || ($dev)-> &pci_device == 0x29d2));
    }' unless defined(&IS_G33);
    eval 'sub IS_I9XX {
        my($dev) = @_;
	    eval q(( &IS_I915G($dev) ||  &IS_I915GM($dev) ||  &IS_I945G($dev) ||  &IS_I945GM($dev) ||  &IS_I965G($dev) ||  &IS_G33($dev)));
    }' unless defined(&IS_I9XX);
    eval 'sub IS_MOBILE {
        my($dev) = @_;
	    eval q(( &IS_I830($dev) ||  &IS_I85X($dev) ||  &IS_I915GM($dev) ||  &IS_I945GM($dev) ||  &IS_I965GM($dev) ||  &IS_GM45($dev)));
    }' unless defined(&IS_MOBILE);
    eval 'sub I915_NEED_GFX_HWS {
        my($dev) = @_;
	    eval q(( &IS_G33($dev) ||  &IS_GM45($dev) ||  &IS_G4X($dev)));
    }' unless defined(&I915_NEED_GFX_HWS);
}
1;
