CMOS 2 CVAX CPU CHIP ENGINEERING SPECIFICATION DC580 21-24674-16 (80nsec) 21-24674-15 (60nsec) Document Rev. 1.0 Chip Rev 2.0 Mask Rev B Contact for SEG: Mike Phipps (RICKS::PHIPPS) C O M P A N Y C O N F I D E N T I A L Copyright (C) 1984, 1985, 1986, 1987, 1988, 1989 by Digital Equipment Corporation The information in this document is subject to change without notice and should not be construed as a commitment by Digital Equipment Corporation. Digital Equipment Corporation assumes no responsibility for any errors that may occur in this document. This specification does not describe any program or product which is currently available from Digital Equipment Corporation. Nor does Digital Equipment Corporation commit to implement this specification in any product or program. Digital Equipment Corporation makes no commitment that this document accurately describes any product it might ever make. CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential)Page 2 TABLE OF CONTENTS CONTENTS 1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . 3 1.1 Scope . . . . . . . . . . . . . . . . . . . . . . 3 1.2 Applicable Documents . . . . . . . . . . . . . . . 3 1.3 CVAX CPU Chip Features . . . . . . . . . . . . . . 3 1.4 Summary Of Differences . . . . . . . . . . . . . . 4 1.5 Part Number Variation Descriptions . . . . . . . . 5 2 ARCHITECTURE SUMMARY . . . . . . . . . . . . . . . . 6 2.1 Visible State . . . . . . . . . . . . . . . . . . 6 2.1.1 Virtual Address Space . . . . . . . . . . . . . 6 2.1.2 Physical Address Space . . . . . . . . . . . . . 7 2.1.3 Registers . . . . . . . . . . . . . . . . . . . 8 2.2 Data Types . . . . . . . . . . . . . . . . . . . . 9 2.3 Instruction Formats And Addressing Modes . . . . 11 2.3.1 Opcode Formats . . . . . . . . . . . . . . . . 11 2.3.2 General Register Operand Specifiers . . . . . 11 2.3.3 Branch Operand Specifiers . . . . . . . . . . 12 2.4 Instruction Set . . . . . . . . . . . . . . . . 13 2.4.1 Integer Arithmetic And Logical Instructions . 14 2.4.2 Address Instructions . . . . . . . . . . . . . 16 2.4.3 Variable Length Bit Field Instructions . . . . 16 2.4.4 Control Instructions . . . . . . . . . . . . . 17 2.4.5 Procedure Call Instructions . . . . . . . . . 18 2.4.6 Miscellaneous Instructions . . . . . . . . . . 18 2.4.7 Queue Instructions . . . . . . . . . . . . . . 19 2.4.8 Character String Instructions . . . . . . . . 19 2.4.9 Operating System Support Instructions . . . . 19 2.4.10 Floating Point Instructions . . . . . . . . . 20 2.4.11 Microcode-Assisted Emulated Instructions . . . 22 2.5 Memory Management . . . . . . . . . . . . . . . 23 2.5.1 Memory Management Control Registers . . . . . 23 2.5.2 System Space Address Translation . . . . . . . 24 2.5.3 Process Space Address Translation . . . . . . 26 2.5.3.1 P0 Region Address Translation . . . . . . . 26 2.5.3.2 P1 Region Address Translation . . . . . . . 28 2.5.4 Page Table Entry . . . . . . . . . . . . . . . 30 2.5.5 Translation Buffer . . . . . . . . . . . . . . 31 2.6 Exceptions And Interrupts . . . . . . . . . . . 32 2.6.1 Interrupts . . . . . . . . . . . . . . . . . . 32 2.6.2 Exceptions . . . . . . . . . . . . . . . . . . 33 2.6.3 System Control Block (SCB) . . . . . . . . . . 34 2.6.4 Machine Check Parameters . . . . . . . . . . . 37 2.6.4.1 Types Of Errors . . . . . . . . . . . . . . 37 2.6.4.2 Machine Check Processing . . . . . . . . . . 40 2.6.4.3 Processor Restart . . . . . . . . . . . . . 41 2.7 Process Structure . . . . . . . . . . . . . . . 43 2.7.1 Process Control Block (PCB) . . . . . . . . . 44 2.8 Processor Registers . . . . . . . . . . . . . . 46 2.8.1 Interval Clock Control And Status Register (ICCS) . . . . . . . . . . . . . . . . . . . . 47 2.8.2 Cache Disable Register (CADR) . . . . . . . . 48 2.8.3 Memory System Error Register (MSER) . . . . . 50 2.8.4 Console Saved Registers (SAVPC, SAVPSL) . . . 50 2.8.5 System Identification Register (SID) . . . . . 51 3 INTERNAL CACHE . . . . . . . . . . . . . . . . . . 52 CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential)Page 3 TABLE OF CONTENTS 3.1 Cache Allocation . . . . . . . . . . . . . . . . 53 3.2 Read Cycle Classification . . . . . . . . . . . 54 3.3 Cache Parity . . . . . . . . . . . . . . . . . 56 3.4 DAL H Parity . . . . . . . . . . . . . . . . . 56 4 INTERFACE . . . . . . . . . . . . . . . . . . . . 57 4.1 Pinouts . . . . . . . . . . . . . . . . . . . . 57 4.1.1 Summary . . . . . . . . . . . . . . . . . . . 57 4.1.2 Data And Address Bus . . . . . . . . . . . . . 58 4.1.2.1 Data And Address Lines (DAL<31:00> H) . . . 58 4.1.2.2 Cycle Status/Data Parity (CS/DP<3:0> L) . . 59 4.1.2.3 Data Parity Enable (DPE L) . . . . . . . . . 60 4.1.3 Bus Control . . . . . . . . . . . . . . . . . 61 4.1.3.1 Address Strobe (AS L) . . . . . . . . . . . 61 4.1.3.2 Data Strobe (DS L) . . . . . . . . . . . . . 61 4.1.3.3 Byte Mask (BM<3:0> L) . . . . . . . . . . . 61 4.1.3.4 Write (WR L) . . . . . . . . . . . . . . . . 62 4.1.3.5 Data Buffer Enable (DBE L) . . . . . . . . . 62 4.1.3.6 Ready (RDY L) . . . . . . . . . . . . . . . 63 4.1.3.7 Error (ERR L) . . . . . . . . . . . . . . . 63 4.1.4 System Control . . . . . . . . . . . . . . . . 64 4.1.4.1 Reset (RESET L) . . . . . . . . . . . . . . 65 4.1.4.2 Halt (HALT L) . . . . . . . . . . . . . . . 65 4.1.5 Interrupt Control . . . . . . . . . . . . . . 65 4.1.5.1 Interrupt Request (IRQ<3:0> L) . . . . . . . 65 4.1.5.2 Power Fail (PWRFL L) . . . . . . . . . . . . 65 4.1.5.3 Corrected Read Data (CRD L) . . . . . . . . 66 4.1.5.4 Interval Timer (INTTIM L) . . . . . . . . . 66 4.1.5.5 Memory Error (MEMERR L) . . . . . . . . . . 66 4.1.6 DMA Control . . . . . . . . . . . . . . . . . 66 4.1.6.1 DMA Request (DMR L) . . . . . . . . . . . . 67 4.1.6.2 DMA Grant (DMG L) . . . . . . . . . . . . . 67 4.1.7 Cache Control (CCTL L) . . . . . . . . . . . . 67 4.1.7.1 Conditional Cache Invalidate . . . . . . . . 67 4.1.7.2 Prevent Data Caching . . . . . . . . . . . . 68 4.1.8 Floating Point Unit Control . . . . . . . . . 68 4.1.8.1 CFPA Data Lines (CPDAT<5:0> H) . . . . . . . 68 4.1.8.2 CFPA Status Lines (CPSTA<1:0> H) . . . . . . 69 4.1.9 Miscellaneous . . . . . . . . . . . . . . . . 72 4.1.9.1 Power . . . . . . . . . . . . . . . . . . . 72 4.1.9.2 Ground . . . . . . . . . . . . . . . . . . . 72 4.1.9.3 Clock In (CLKA,CLKB) . . . . . . . . . . . . 72 4.1.9.4 Clear Write Buffer (CWB L) . . . . . . . . . 72 4.1.9.5 Test (TEST H) . . . . . . . . . . . . . . . 73 4.2 Bus Cycle Descriptions . . . . . . . . . . . . . 73 4.2.1 Idle Cycle . . . . . . . . . . . . . . . . . . 74 4.2.2 Single Transfer CPU Read Cycle . . . . . . . . 74 4.2.3 Multiple Transfer CPU Read Cycle . . . . . . . 75 4.2.4 CPU Write Cycle . . . . . . . . . . . . . . . 77 4.2.5 External Processor Register Read Cycle . . . . 78 4.2.6 External Processor Register Write Cycle . . . 79 4.2.7 Interrupt Acknowledge Cycle . . . . . . . . . 80 4.2.8 DMA Grant Cycle . . . . . . . . . . . . . . . 80 4.2.9 Cache Invalidate Cycles . . . . . . . . . . . 81 4.3 Memory Access Protocol . . . . . . . . . . . . . 81 4.3.1 I-stream Prefetching . . . . . . . . . . . . . 83 4.4 CFPA Protocols . . . . . . . . . . . . . . . . . 83 CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential)Page 4 TABLE OF CONTENTS 4.4.1 Passing Opcode Information To The CFPA . . . . 83 4.4.2 Passing Operands To The CFPA . . . . . . . . . 84 4.4.3 Passing Results Back From The CFPA . . . . . . 84 4.4.4 CFPA Present Indication . . . . . . . . . . . 86 4.4.5 CFPA Forced Termination . . . . . . . . . . . 86 4.4.6 CFPA Interface Overhead . . . . . . . . . . . 87 4.4.6.1 Opcode Transfer . . . . . . . . . . . . . . 87 4.4.6.2 Passing Operands To CFPA . . . . . . . . . . 88 4.4.6.3 Passing Results Back From CFPA . . . . . . . 89 4.5 Test Logic . . . . . . . . . . . . . . . . . . . 90 4.5.1 Observability Logic . . . . . . . . . . . . . 90 4.5.2 Control Logic . . . . . . . . . . . . . . . . 91 4.5.3 Normal State . . . . . . . . . . . . . . . . . 91 4.5.4 Test State . . . . . . . . . . . . . . . . . . 91 4.5.4.1 Internal MAB . . . . . . . . . . . . . . . . 91 4.5.4.2 External MAB . . . . . . . . . . . . . . . . 92 4.5.4.3 Force Broadcast . . . . . . . . . . . . . . 92 4.5.5 Test Registers . . . . . . . . . . . . . . . . 92 4.5.6 Main Reducer . . . . . . . . . . . . . . . . . 92 4.5.7 Test Control Pins Allocation . . . . . . . . . 93 5 DC CHARACTERISTICS . . . . . . . . . . . . . . . . 94 5.1 Electrostatic Discharge . . . . . . . . . . . . 94 5.2 Absolute Maximum Ratings . . . . . . . . . . . . 94 5.3 Electrical Characteristics . . . . . . . . . . . 94 5.4 Signal Summary . . . . . . . . . . . . . . . . . 96 6 AC CHARACTERISTICS . . . . . . . . . . . . . . . . 99 6.1 80nS Input Requirements (21-24674-16) . . . . . 99 6.2 80nS Output Responses (21-24674-16) . . . . . . 101 6.3 60nS Input Requirements (21-24674-15) . . . . . 103 6.4 60nS Output Responses (21-24674-15) . . . . . . 105 7 TIMING DIAGRAMS . . . . . . . . . . . . . . . . . 107 7.1 Clock Timing Requirements . . . . . . . . . . . 107 7.2 Initialization . . . . . . . . . . . . . . . . . 108 7.3 CWB L And TEST L Timing . . . . . . . . . . . . 109 7.4 External Interrupt Timing . . . . . . . . . . . 110 7.5 External DMA Timing . . . . . . . . . . . . . . 111 7.6 Quadword Cache Invalidate Cycle . . . . . . . . 112 7.7 Octaword Cache Invalidate Cycle . . . . . . . . 113 7.8 Single Transfer CPU Read Cycle, Interrupt Acknowledge Cycle . . . . . . . . . . . . . . . 114 7.9 Multiple Transfer CPU Read Cycle . . . . . . . . 117 7.10 CPU Write Cycle . . . . . . . . . . . . . . . . 120 7.11 CFPA Interface Timing . . . . . . . . . . . . . 123 7.11.1 Opcode Transfers . . . . . . . . . . . . . . . 123 7.11.2 Single Precision CVAX CPU To CFPA Transfer . . 124 7.11.3 Double Precision CVAX CPU To CFPA Transfer . . 125 7.11.4 Single Precision CFPA To CVAX CPU Transfers . 126 7.11.5 Double Precision CFPA To CVAX CPU Transfers . 128 8 CHIP INTERCONNECT DIAGRAM . . . . . . . . . . . . 130 9 DIFFERENCES BETWEEN CVAX DC341/DC580 AND MICROVAX DC333 . . . . . . . . . . . . . . . . . . . . . . 131 9.1 SOFTWARE DIFFERENCES . . . . . . . . . . . . . . 131 9.2 HARDWARE DIFFERENCES . . . . . . . . . . . . . . 132 10 PACKAGE PINOUT . . . . . . . . . . . . . . . . . . 135 11 BONDING PINOUT . . . . . . . . . . . . . . . . . . 136 12 CVAX INSTRUCTION TIMING . . . . . . . . . . . . . 137 CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential)Page 5 TABLE OF CONTENTS 12.1 Specifier Timing . . . . . . . . . . . . . . . . 138 12.1.1 Specifier Timing (Not The Last Specifier) . . 138 12.1.2 Specifier Timing (Last Specifier) . . . . . . 139 12.2 Execute, Fetch Timing . . . . . . . . . . . . . 141 12.2.1 Integer Arithmetic And Logical Instructions . 141 12.2.2 Address Instructions . . . . . . . . . . . . . 144 12.2.3 Variable Length Bit Field Instructions . . . . 145 12.2.4 Control Instructions . . . . . . . . . . . . . 145 12.2.5 Procedure Call Instructions . . . . . . . . . 147 12.2.6 Miscellaneous Instructions . . . . . . . . . . 147 12.2.7 Queue Instructions . . . . . . . . . . . . . . 148 12.2.8 Character String Instructions . . . . . . . . 148 12.2.9 Operating System Support Instructions . . . . 149 12.2.10 Floating Point Instructions . . . . . . . . . 149 12.2.11 Microcode-Assisted Emulated Instructions . . . 151 12.3 Other Timings . . . . . . . . . . . . . . . . . 153 12.4 Examples . . . . . . . . . . . . . . . . . . . . 154 CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 6 REVISION HISTORY REVISION HISTORY ---------------- REV DATE REASON --- ---- ------ 1.0 13-Jan-88 Creation of the DC580 Engineering Specification. This Specification reflects the functionality implemented in the 2nd pass CMOS-2 part. SPECIFIC CHANGES ------------------ Section 1.5 reflects the last known restriction (Reboot on ERR & cache miss and the last microcode change (MFPR bug). NOTE The following milestones are included for continuity purposes. For complete data refer to the "CVAX CPU Chip Engineering Specification - DC341" REV DATE REASON --- ---- ------ 4.0 9-Jun-88 This specification reflects the functionality implemented on the 4th pass part. 3.0 27-May-87 This specification reflects the functionality implemented on the 3rd pass part. 2.0 8-Dec-86 This specification reflects the functionality implemented on the 2nd pass part. 1.00 11-Nov-84 Preliminary version. CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 7 INTRODUCTION 1 INTRODUCTION 1.1 Scope This document describes the CVAX CPU chip, a CMOS/VLSI chip that implements a VAX central processor. This specification describes the external interface and behavior of the chip. It does not describe the internal organization or operation of the chip. For further information, the applicable documents should be consulted. 1.2 Applicable Documents VAX Architecture Standard (DEC Standard 032) CVAX CPU Chip Design Specification CVAX CPU Chip Engineering Specification - DC341 CVAX Clock Chip Engineering Specification CMOS 2 CFPA Chip (DC581) Engineering Specification 1.3 CVAX CPU Chip Features The CVAX DC580 CPU chip is a 32-bit, virtual memory microprocessor. Implemented in CMOS-2 (`1.5 micron' double metal CMOS), the 180K transistor CVAX CPU chip is a high performance, low cost CPU for single board computers, single user workstations, low end systems, and multiple microprocessor systems. The DC580 is functionally equivalent to and pin-compatible with the DC341 CMOS I CVAX CPU. The DC580 has a higher performance figure than the DC341. Key features of the CVAX CPUs are: 1. Subset VAX data types. The CVAX CPU chip supports the following subset of the VAX data types: byte, word, longword, quadword, character string, and variable length bit field. Support for f_floating, d_floating, and g_floating data types is provided by an external Floating Point Coprocessor. Support for the remaining VAX data types can be provided by macrocode emulation. 2. Full base instruction group. The CVAX CPU chip implements the full base instruction group which consists of the following VAX instruction: integer and logical, address, variable length bit field, control, procedure call, miscellaneous, queue, CMPC3/CMPC5, LOCC, MOVC3/MOVC5, SCANC, SKPC, SPANC and operating system support. f_floating point, d_floating point, and g_floating point instructions are implemented in an external floating point unit (including the floating point instructions that are part of the CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 8 INTRODUCTION emulate-only instruction group: POLYf, EMULf, and ACBf). The remaining VAX instructions can be implemented via macrocode emulation (the CVAX CPU chip provides microcode assists for the emulation of character string instructions not included in the full base instruction group, decimal string, EDITPC, and CRC instructions). 3. Full VAX memory management. The CVAX CPU chip includes a demand paged memory management unit which is fully compatible with VAX memory management. System space addresses are virtually mapped through single level page tables, process space addresses through double level page tables. 4. On chip cache. The CVAX CPU chip includes 1k bytes of on chip cache to optimize the performance of the memory subsystem. The cache can be configured to store I-stream only references, or both I-stream and D-stream references. 5. The external interface is based on industry Standards. The CVAX CPU chip's external interface is a 32-bit custom implementation of the industry standard microprocessor interface. The CVAX CPU chip functionally replaces the MicroVAX CPU chip in existing designs although the exact timing, pin assignments, and external protocol have slightly changed. Chapter 9 highlights the interface differences between MicroVAX and CVAX. 6. Large virtual and physical address space. The CVAX CPU chip supports four gigabytes (2**32) of virtual memory, and one gigabyte (2**30) of physical memory. 7. High performance. The 21-24674-15 CVAX CPU chip achieves a 60 nsec microcycle and a 120 nsec I/O cycle. 8. Single package. The CVAX CPU chip is packaged in a standard 84-pin surface mounted chip carrier. 1.4 Summary Of Differences The principal differences between the CVAX CPU chip and the full VAX architecture are these: 1. The CVAX CPU chip omits these data types: decimal string, octaword, h_floating. [These data types can be supported via macrocode emulation.] 2. The CVAX CPU chip omits these instruction classes: character string instructions (MATCHC, MOVTC, MOVTUC), decimal string, EDITPC, CRC, compatibility mode, octaword, h_floating. [The chip provides microcode assists for the macrocode emulation of the character string, decimal string, CRC, and EDITPC instructions.] CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 9 INTRODUCTION 3. The CVAX CPU chip omits some of the VAX internal processor registers. Specifically, NICR, ICR, TODR, RXCS, RXDB, TXCS, TXDB and PMR are not built in CVAX. MFPR or MTPR references to these registers generate an external processor register read or write cycle, respectively. Therefore, these registers can be externally supported. 4. The CVAX CPU chip does not have a built-in console function. 1.5 Part Number Variation Descriptions Digital Part # Mask Letter/Rev Speed Restriction 21-24674-16 B / PASS 2.0 80nS Yes 21-24674-15 B / PASS 2.0 60nS Yes Restrictions: When operating correctly, if external logic asserts ERR L in response to any memory cycle other than an instruction prefetch or interrupt acknowledge, a machine check occurs. If a write error occurs that does not satisfy the problem conditions, a machine check is followed by execution of system error (macro)code. The error code will determine if a system reboot is needed. If the problem conditions are met, a immediate reboot with no machine check is the result. The restart code will be 3, initial power on. When a specific sequence of events combines with a write cycle and the write cycle ends with an error response, the CVAX will be forced to branch to the restart microcode (an error response is ERRL asserted and RDYL not asserted for two sample points). The problem can only occur when writing to memory or IO space. It does not occur when writing to an IPR and does not occur if the MEMERRL or CRDL interrupt inputs are asserted. The probability of the problem occurring are extremely small and occurs under the following specific circumstances: 1. Write is queued up in Bus Interface Unit (BIU) 2. The second sample point of an ERRL response to the write operation is seen at the same time as the start of a non-prefetch data read. 3. The above data read will result in a cache miss. If the read operation starts one cycle earlier or later, no problem occurs. If the read is an instruction prefetch, no problem occurs. If the read does not cause a cache miss, no problem occurs. CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 10 ARCHITECTURE SUMMARY 2 ARCHITECTURE SUMMARY This section provides summary information about the architecture of the CVAX CPU chip. It is not intended as a complete reference but rather to give an overview of the user-visible features. For a complete description of the architecture, consult the "VAX Architecture Standard". 2.1 Visible State The visible state of the processor consists of memory, both virtual and physical, the general registers, and the processor status longword (PSL). 2.1.1 Virtual Address Space - The virtual address space is four gigabytes (2**32), as follows: +-------------------------+ 00000000 | | length of P0 Region in pages (P0LR) | | | P0 ----------------| | Region | | 3FFFFFFF | V | P0 Region growth direction +-------------------------+ 40000000 | ^ | P1 Region growth direction | | | | P1 ----------------| | Region | 7FFFFFFF | | length of P1 Region in pages (2**21-P1LR) +-------------------------+ 80000000 | | length of System Region in pages (SLR) | | | System ---------------| | Region | | BFFFFFFF | V | System Region growth direction +-------------------------+ C0000000 | | | | | Reserved | | Region | FFFFFFFF | | +-------------------------+ CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 11 ARCHITECTURE SUMMARY 2.1.2 Physical Address Space - The physical address space is one gigabyte (2**30), as follows: +-------------------------+ 00000000 | | | | | Memory | | Space | | | 1FFFFFFF | | +-------------------------+ 20000000 | | | | | I/O | | Space | | | 3FFFFFFF | | +-------------------------+ CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 12 ARCHITECTURE SUMMARY 2.1.3 Registers - 3 1 0 +---------------------------------------------------------------+ 16 general registers | | :Rn [R0 - R11, general purpose +---------------------------------------------------------------+ R12 = AP, argument pointer R13 = FP, frame pointer R14 = SP, stack pointer R15 = PC, program counter] 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 6 5 8 7 6 5 4 3 2 1 0 +-+-+---+-+-+---+---+-+---------+---------------+-+-+-+-+-+-+-+-+ | | | |F| | | |M| | | | | | | | | | | Processor Status Longword |C|T| |P|I|CUR|PRV|B| | |D|F|I| | | | | | :PSL [CM = compatibility mode |M|P|MBZ|D|S|MOD|MOD|Z| IPL | MBZ |V|U|V|T|N|Z|V|C| TP = trace pending +-+-+---+-+-+---+---+-+---------+---------------+-+-+-+-+-+-+-+-+ FPD = first part done IS = interrupt stack CUR = current mode PRV = previous mode IPL = interrupt priority level DV = decimal overflow trap enable FU = floating underflow fault enable IV = integer overflow trap enable T = trace trap enable N = negative condition code Z = zero condition code V = overflow condition code C = carry condition code] CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 13 ARCHITECTURE SUMMARY 2.2 Data Types The CVAX CPU chip supports nine data types: byte, word, longword, quadword, character string, variable length bit field, and, through an optional external processor, f_floating, d_floating, and g_floating. These are summarized below: Type Length Use Graphic Representation ---- ------ --- ------------------------ 7 0 +---------------+ Byte 8 bits signed or | | :A unsigned integer +---------------+ 1 5 0 +-------------------------------+ Word 16 bits signed or | | :A unsigned integer +-------------------------------+ 3 1 0 +---------------------------------------------------------------+ Longword 32 bits signed or | | :A unsigned integer +---------------------------------------------------------------+ 3 1 0 +---------------------------------------------------------------+ Quadword 64 bits signed integer | | :A +---------------------------------------------------------------+ | | :A+4 +---------------------------------------------------------------+ 6 3 3 2 7 0 +---------------+ Character 0-65k bytes byte string | | :A String +---------------+ | | :A+1 +---------------+ . . . +---------------+ | | :A+L-1 +---------------+ 7 0 CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 14 ARCHITECTURE SUMMARY P+S P+S-1 P P-1 0 +---------------------+------------------+----------------------+ Variable Length 0-32 bits bit string | |//////////////////| | :A Bit Field +---------------------+------------------+----------------------+ S-1 0 1 1 5 4 7 6 0 +-+---------------+-------------+ F_floating 32 bits floating point |S| exponent | fraction | :A +-+---------------+-------------+ | fraction | :A+2 +-------------------------------+ 3 1 1 6 1 1 5 4 7 6 0 +-+---------------+-------------+ D_floating 64 bits floating point |S| exponent | fraction | :A +-+---------------+-------------+ | fraction | :A+2 +-------------------------------+ | fraction | :A+4 +-------------------------------+ | fraction | :A+6 +-------------------------------+ 6 4 3 8 1 1 5 4 4 3 0 +-+---------------------+-------+ G_floating 64 bits floating point |S| exponent | frac | :A +-+---------------------+-------+ | fraction | :A+2 +-------------------------------+ | fraction | :A+4 +-------------------------------+ | fraction | :A+6 +-------------------------------+ 6 4 3 8 CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 15 ARCHITECTURE SUMMARY 2.3 Instruction Formats And Addressing Modes VAX instructions consist of a one- or two-byte opcode, followed by zero to six operand specifiers. 2.3.1 Opcode Formats - 7 0 +---------------+ One byte opcode: | opcode | :A +---------------+ 1 5 8 7 0 +---------------+---------------+ Two byte opcode: | opcode | FD | :A +---------------+---------------+ 2.3.2 General Register Operand Specifiers - The general register address modes are: 7 4 3 0 +-------+-------+ | mode | reg | +-------+-------+ Access Mode Name Assembler r m w a v PC SP Indexable? ---- ---- --------- --------- -- -- ---------- 0-3 literal S^#literal y f f f f - - f 4 index i[Rx] y y y y y f y f 5 register Rn y y y f y u uq f 6 register deferred (Rn) y y y y y u y y 7 autodecrement -(Rn) y y y y y u y ux 8 autoincrement (Rn)+ y y y y y p y ux 9 autoincrement @(Rn)+ y y y y y p y ux deferred A byte displacement B^d(Rn) y y y y y p y y B byte displacement @B^d(Rn) y y y y y p y y deferred C word displacement W^d(Rn) y y y y y p y y D word displacement @W^d(Rn) y y y y y p y y deferred E longword displacement L^d(Rn) y y y y y p y y F longword displacement @L^d(Rn) y y y y y p y y deferred CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 16 ARCHITECTURE SUMMARY If the register is the PC, the address modes are: 7 4 3 0 +-------+-------+ | mode |1 1 1 1| +-------+-------+ Access Mode Name Assembler r m w a v Indexable? ---- ---- --------- --------- ---------- 8 Immediate I^#constant y u u y y u 9 absolute @#address y y y y y y A byte relative B^address y y y y y y B byte relative @B^address y y y y y y deferred C word relative W^address y y y y y y D word relative W^address y y y y y y deferred E longword relative L^address y y y y y y F longword relative L^address y y y y y y deferred Addressing Legend Access: Syntax: Results: r = read i = any Indexable address mode y = yes, always valid address mode m = modify d = displacement f = reserved address mode fault w = write Rn = general register, n = to 15 - = logically impossible a = address Rx = general register, x = to 14 p = program counter addressing v = field u = unpredictable uq = unpredictable for quad, d/g_floating, and field if pos + size > 32 ux = unpredictable if index reg = base reg 2.3.3 Branch Operand Specifiers - 7 0 +---------------+ Signed byte displacement: | displ | +---------------+ 1 5 0 +-------------------------------+ Signed word displacement: | displ | +-------------------------------+ CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 17 ARCHITECTURE SUMMARY 2.4 Instruction Set The standard notation for operand specifiers is: . where: 1. Name is a suggestive name for the operand in the context of the instruction. It is the capitalized name of a register or block for implied operands. 2. Access type is a letter denoting the operand specifier access type. a = address operand b = branch displacement m = modified operand (both read and written) r = read only operand v = if not "Rn", same as a, otherwise R[n+1]'R[n] w = write only operand 3. Data type is a letter denoting the data type of the operand. b = byte d = d_floating f = f_floating g = g_floating l = longword q = quadword v = field (used only in implied operands) w = word * = multiple longwords (used only in implied operands) 4. Implied operands, that is, locations that are accessed by the instruction, but not specified in an operand, are denoted by curly braces {}. The abbreviations for condition codes are: * = conditionally set/cleared - = not affected 0 = cleared 1 = set The abbreviations for exceptions are: rsv = reserved operand fault iov = integer overflow trap idvz = integer divide by zero trap fov = floating overflow fault fuv = floating underflow fault fdvz = floating divide by zero fault dov = decimal overflow trap ddvz = decimal divide by zero trap sub = subscript range trap CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 18 ARCHITECTURE SUMMARY prv = privileged instruction fault 2.4.1 Integer Arithmetic And Logical Instructions - Opcode Instruction N Z V C Exceptions ------ ----------- ------- ---------- 58 ADAWI add.rw, sum.mw * * * * iov 80 ADDB2 add.rb, sum.mb * * * * iov C0 ADDL2 add.rl, sum.ml * * * * iov A0 ADDW2 add.rw, sum.mw * * * * iov 81 ADDB3 add1.rb, add2.rb, sum.wb * * * * iov C1 ADDL3 add1.rl, add2.rl, sum.wl * * * * iov A1 ADDW3 add1.rw, add2.rw, sum.ww * * * * iov D8 ADWC add.rl, sum.ml * * * * iov 78 ASHL cnt.rb, src.rl, dst.wl * * * 0 iov 79 ASHQ cnt.rb, src.rq, dst.wq * * * 0 iov 8A BICB2 mask.rb, dst.mb * * 0 - CA BICL2 mask.rl, dst.ml * * 0 - AA BICW2 mask.rw, dst.mw * * 0 - 8B BICB3 mask.rb, src.rb, dst.wb * * 0 - CB BICL3 mask.rl, src.rl, dst.wl * * 0 - AB BICW3 mask.rw, src.rw, dst.ww * * 0 - 88 BICB2 mask.rb, dst.mb * * 0 - C8 BISL2 mask.rl, dst.ml * * 0 - A8 BISW2 mask.rw, dst.mw * * 0 - 89 BISB3 mask.rb, src.rb, dst.wb * * 0 - C9 BISL3 mask.rl, src.rl, dst.wl * * 0 - A9 BISW3 mask.rw, src.rw, dst.ww * * 0 - 93 BITB mask.rb, src.rb * * 0 - D3 BITL mask.rl, src.rl * * 0 - B3 BITW mask.rw, src.rw * * 0 - 94 CLRB dst.wb 0 1 0 - D4 CLRL{=F} dst.wl 0 1 0 - 7C CLRQ{=D=G} dst.wq 0 1 0 - B4 CLRW dst.ww 0 1 0 - 91 CMPB src1.rb, src2.rb * * 0 * D1 CMPL src1.rl, src2.rl * * 0 * B1 CMPW src1.rw, src2.rw * * 0 * 98 CVTBL src.rb, dst.wl * * 0 0 99 CVTBW src.rb, dst.wl * * 0 0 CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 19 ARCHITECTURE SUMMARY F6 CVTLB src.rl, dst.wb * * * 0 iov F7 CVTLW src.rl, dst.ww * * * 0 iov 33 CVTWB src.rw, dst.wb * * * 0 iov 32 CVTWL src.rw, dst.wl * * 0 0 97 DECB dif.mb * * * * iov D7 DECL dif.ml * * * * iov B7 DECW dif.mw * * * * iov 86 DIVB2 divr.rb, quo.mb * * * 0 iov, idvz C6 DIVL2 divr.rl, quo.ml * * * 0 iov, idvz A6 DIVW2 divr.rw, quo.mw * * * 0 iov, idvz 87 DIVB3 divr.rb, divd.rb, quo.wb * * * 0 iov, idvz C7 DIVL3 divr.rl, divd.rl, quo.wl * * * 0 iov, idvz A7 DIVW3 divr.rw, divd.rw, quo.ww * * * 0 iov, idvz 7B EDIV divr.rl, divd.rq, quo.wl, rem.wl * * * 0 iov, idvz 7A EMUL mulr.rl, muld.rl, add.rl, prod.wq * * 0 0 96 INCB sum.mb * * * * iov D6 INCL sum.ml * * * * iov B6 INCW sum.mw * * * * iov 92 MCOMB src.rb, dst.wb * * 0 - D2 MCOML src.rl, dst.wl * * 0 - B2 MCOMW src.rw, dst.ww * * 0 - 8E MNEGB src.rb, dst.wb * * * * iov CE MNEGL src.rl, dst.wl * * * * iov AE MNEGW src.rw, dst.ww * * * * iov 90 MOVB src.rb, dst.wb * * 0 - D0 MOVL src.rl, dst.wl * * 0 - 7D MOVQ src.rq, dst.wq * * 0 - B0 MOVW src.rw, dst.ww * * 0 - 9A MOVZBW src.rb, dst.wb 0 * 0 - 9B MOVZBL src.rb, dst.wl 0 * 0 - 3C MOVZWL src.rw, dst.ww 0 * 0 - 84 MULB2 mulr.rb, prod.mb * * * 0 iov C4 MULL2 mulr.rl, prod.ml * * * 0 iov A4 MULW2 mulr.rw, prod.mw * * * 0 iov 85 MULB3 mulr.rb, muld.rb, prod.wb * * * 0 iov C5 MULL3 mulr.rl, muld.rl, prod.wl * * * 0 iov A5 MULW3 mulr.rw, muld.rw, prod.ww * * * 0 iov DD PUSHL src.rl, {-(SP).wl} * * 0 - 9C ROTL cnt.rb, src.rl, dst.wl * * 0 - D9 SBWC sub.rl, dif.ml * * * * iov CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 20 ARCHITECTURE SUMMARY 82 SUBB2 sub.rb, dif.mb * * * * iov C2 SUBL2 sub.rl, dif.ml * * * * iov A2 SUBW2 sub.rw, dif.mw * * * * iov 83 SUBB3 sub.rb, min.rb, dif.wb * * * * iov C3 SUBL3 sub.rl, min.rl, dif.wl * * * * iov A3 SUBW3 sub.rw, min.rw, dif.ww * * * * iov 95 TSTB src.rb * * 0 0 D5 TSTL src.rl * * 0 0 B5 TSTW src.rw * * 0 0 8C XORB2 mask.rb, dst.mb * * 0 - CC XORL2 mask.rl, dst.ml * * 0 - AC XORB2 mask.rw, dst.mw * * 0 - 8D XORB3 mask.rb, src.rb, dst.wb * * 0 - CD XORL3 mask.rl, src.rl, dst.wl * * 0 - AD XORW3 mask.rw, src.rw, dst.ww * * 0 - 2.4.2 Address Instructions - Opcode Instruction N Z V C Exceptions ------ ----------- ------- ---------- 9E MOVAB src.ab, dst.wl * * 0 - DE MOVAL{=F} src.al, dst.wl * * 0 - 7E MOVAQ{=D=G} src.aq, dst.wl * * 0 - 3E MOVAW src.aw, dst.wl * * 0 - 9F PUSHAB src.ab, {-(SP).wl} * * 0 - DF PUSHAL{=F} src.al, {-(SP).wl} * * 0 - 7F PUSHAQ{=D=G} src.aq, {-(SP).wl} * * 0 - 3F PUSHAW src.aw, {-(SP).wl} * * 0 - 2.4.3 Variable Length Bit Field Instructions - Opcode Instruction N Z V C Exceptions ------ ----------- ------- ---------- EC CMPV pos.rl, size.rb, base.vb, {field.rv}, src.rl * * 0 * rsv ED CMPZV pos.rl, size.rb, base.vb, {field.rv}, src.rl * * 0 * rsv EE EXTV pos.rl, size.rb, base.vb, {field.rv}, dst.wl * * 0 - rsv EF EXTZV pos.rl, size.rb, base.vb, {field.rv}, dst.wl * * 0 - rsv F0 INSV src.rl, pos.rl, size.rb, base.vb, {field.wv} - - - - rsv CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 21 ARCHITECTURE SUMMARY EB FFC startpos.rl, size.rb, base.vb, {field.rv}, findpos.wl 0 * 0 0 rsv EA FFS startpos.rl, size.rb, base.vb, {field.rv}, findpos.wl 0 * 0 0 rsv 2.4.4 Control Instructions - Opcode Instruction N Z V C Exceptions ------ ----------- ------- ---------- 9D ACBB limit.rb, add.rb, index.mb, displ.bw * * * - iov F1 ACBL limit.rl, add.rl, index.ml, displ.bw * * * - iov 3D ACBW limit.rw, add.rw, index.mw, displ.bw * * * - iov F3 AOBLEQ limit.rl, index.ml, displ.bb * * * - iov F2 AOBLSS limit.rl, index.ml, displ.bb * * * - iov 1E BCC{=BGEQU} displ.bb - - - - 1F BCS{=BLSSU} displ.bb - - - - 13 BEQL{=BEQLU} displ.bb - - - - 18 BGEQ displ.bb - - - - 14 BGTR displ.bb - - - - 1A BGTRU displ.bb - - - - 15 BLEQ displ.bb - - - - 1B BLEQU displ.bb - - - - 19 BLSS displ.bb - - - - 12 BNEQ{=BNEQU} displ.bb - - - - 1C BVC displ.bb - - - - 1D BVS displ.bb - - - - E1 BBC pos.rl, base.vb, displ.bb, {field.rv} - - - - rsv E0 BBS pos.rl, base.vb, displ.bb, {field.rv} - - - - rsv E5 BBCC pos.rl, base.vb, displ.bb, {field.mv} - - - - rsv E3 BBCS pos.rl, base.vb, displ.bb, {field.mv} - - - - rsv E4 BBSC pos.rl, base.vb, displ.bb, {field.mv} - - - - rsv E2 BBSS pos.rl, base.vb, displ.bb, {field.mv} - - - - rsv E7 BBCCI pos.rl, base.vb, displ.bb, {field.mv} - - - - rsv E6 BBSSI pos.rl, base.vb, displ.bb, {field.mv} - - - - rsv E9 BLBC src.rl, displ.bb - - - - E8 BLBS src.rl, displ.bb - - - - 11 BRB displ.bb - - - - 31 BRW displ.bw - - - - 10 BSBB displ.bb, {-(SP).wl} - - - - 30 BSBW displ.bw, {-(SP).wl} - - - - 8F CASEB selector.rb, base.rb, limit.rb, displ.bw-list * * 0 * CF CASEL selector.rl, base.rl, limit.rl, displ.bw-list * * 0 * AF CASEW selector.rw, base.rw, limit.rw, displ.bw-list * * 0 * CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 22 ARCHITECTURE SUMMARY 17 JMP dst.ab - - - - 16 JSB dst.ab, {-(SP).wl} - - - - 05 RSB {(SP)+.rl} - - - - F4 SOBGEQ index.ml, displ.bb * * * - iov F5 SOBGTR index.ml, displ.bb * * * - iov 2.4.5 Procedure Call Instructions - Opcode Instruction N Z V C Exceptions ------ ----------- ------- ---------- FA CALLG arglist.ab, dst.ab, {-(SP).w*} 0 0 0 0 rsv FB CALLS numarg.rl, dst.ab, {-(SP).w*} 0 0 0 0 rsv 04 RET {(SP)+.r*} * * * * rsv 2.4.6 Miscellaneous Instructions - Opcode Instruction N Z V C Exceptions ------ ----------- ------- ---------- B9 BICPSW mask.rw * * * * rsv B8 BISPSW mask.rw * * * * rsv 03 BPT {-(KSP).w*} 0 0 0 0 00 HALT {-(KSP).w*} - - - - prv 0A INDEX subscript.rl, low.rl, high.rl, size.rl, indexin.rl, * * 0 0 sub indexout.wl DC MOVPSL dst.wl - - - - 01 NOP - - - - BA POPR mask.rw, {(SP)+.r*} - - - - BB PUSHR mask.rw, {-(SP).w*} - - - - FC XFC {unspecified operands} 0 0 0 0 CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 23 ARCHITECTURE SUMMARY 2.4.7 Queue Instructions - Opcode Instruction N Z V C Exceptions ------ ----------- ------- ---------- 5C INSQHI entry.ab, header.aq 0 * 0 * rsv 5D INSQTI entry.ab, header.aq 0 * 0 * rsv 0E INSQUE entry.ab, pred.ab * * 0 * 5E REMQHI header.aq, addr.wl 0 * * * rsv 5F REMQTI header.aq, addr.wl 0 * * * rsv 0F REMQUE entry.ab, addr.wl * * * * 2.4.8 Character String Instructions - Opcode Instruction N Z V C Exceptions ------ ----------- ------- ---------- 29 CMPC3 len.rw, src1addr.ab, src2addr.ab * * 0 * 2D CMPC5 src1len.rw, src1addr.ab, fill.rb, * * 0 * src2len.rw, src2addr.ab 3A LOCC char.rb, len.rw, addr.ab 0 * 0 0 28 MOVC3 len.rw, srcaddr.ab, dstaddr.ab, {R0-5.wl} 0 1 0 0 2C MOVC5 srclen.rw, srcaddr.ab, fill.rb, dstlen.rw, dstaddr.ab, * * 0 * {R0-5.wl} 2A SCANC len.rw, addr.ab, tbladdr.ab, mask.rb 0 * 0 0 3B SKPC char.rb, len.rw, addr.ab 0 * 0 0 2B SPANC len.rw, addr.ab, tbladdr.ab, mask.rb 0 * 0 0 2.4.9 Operating System Support Instructions - Opcode Instruction N Z V C Exceptions ------ ----------- ------- ---------- BD CHME param.rw, {-(ySP).w*} 0 0 0 0 BC CHMK param.rw, {-(ySP).w*} 0 0 0 0 BE CHMS param.rw, {-(ySP).w*} 0 0 0 0 CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 24 ARCHITECTURE SUMMARY BF CHMU param.rw, {-(ySP).w*} 0 0 0 0 Where y=MINU(x, PSL) 06 LDPCTX {PCB.r*, -(KSP).w*} - - - - rsv, prv DB MFPR procreg.rl, dst.wl * * 0 - rsv, prv DA MTPR src.rl, procreg.rl * * 0 - rsv, prv 0C PROBER mode.rb, len.rw, base.ab 0 * 0 - 0D PROBEW mode.rb, len.rw, base.ab 0 * 0 - 02 REI {(SP)+.r*} * * * * rsv 07 SVPCTX {(SP)+.r*, PCB.w*} - - - - prv 2.4.10 Floating Point Instructions - These instructions are implemented in hardware only if an external floating point unit is present in the system. Opcode Instruction N Z V C Exceptions ------ ----------- ------- ---------- 6F ACBD limit.rd, add.rd, index.md,displ.bw * * 0 - rsv, fov, fuv 4F ACBF limit.rf, add.rf, index.mf,displ.bw * * 0 - rsv, fov, fuv 4FFD ACBG limit.rg, add.rg, index.mg,displ.bw * * 0 - rsv, fov, fuv 60 ADDD2 add.rd, sum.md * * 0 0 rsv, fov, fuv 40 ADDF2 add.rf, sum.mf * * 0 0 rsv, fov, fuv 40FD ADDG2 add.rg, sum.mg * * 0 0 rsv, fov, fuv 61 ADDD3 add1.rd, add2.rd, sum.wd * * 0 0 rsv, fov, fuv 41 ADDF3 add1.rf, add2.rf, sum.wf * * 0 0 rsv, fov, fuv 41FD ADDG3 add1.rg, add2.rg, sum.wg * * 0 0 rsv, fov, fuv 71 CMPD src1.rd, src2.rd * * 0 0 rsv 51 CMPF src1.rf, src2.rf * * 0 0 rsv 51FD CMPG src1.rg, src2.rg * * 0 0 rsv 6C CVTBD src.rb, dst.wd * * 0 0 4C CVTBF src.rb, dst.wf * * 0 0 4CFD CVTBG src.rb, dst.wg * * 0 0 68 CVTDB src.rd, dst.wb * * * 0 rsv, iov 76 CVTDF src.rd, dst.wf * * 0 0 rsv, fov 6A CVTDL src.rd, dst.wl * * * 0 rsv, iov 69 CVTDW src.rd, dst.ww * * * 0 rsv, iov 48 CVTFB src.rf, dst.wb * * * 0 rsv, iov 56 CVTFD src.rf, dst.wd * * 0 0 rsv 99FD CVTFG src.rf, dst.wg * * 0 0 rsv 4A CVTFL src.rf, dst.wl * * * 0 rsv, iov 49 CVTFW src.rf, dst.ww * * * 0 rsv, iov 48FD CVTGB src.rg, dst.wb * * * 0 rsv, iov 33FD CVTGF src.rg, dst.wf * * 0 0 rsv, fov, fuv CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 25 ARCHITECTURE SUMMARY 4AFD CVTGL src.rg, dst.wl * * * 0 rsv, iov 49FD CVTGW src.rg, dst.ww * * * 0 rsv, iov 6E CVTLD src.rl, dst.wd * * 0 0 4E CVTLF src.rl, dst.wf * * 0 0 4EFD CVTLG src.rl, dst.wg * * 0 0 6D CVTWD src.rw, dst.wd * * 0 0 4D CVTWF src.rw, dst.wf * * 0 0 4DFD CVTWG src.rw, dst.wg * * 0 0 6B CVTRDL src.rd, dst.wl * * * 0 rsv, iov 4B CVTRFL src.rf, dst.wl * * * 0 rsv, iov 4BFD CVTRGL src.rg, dst.wl * * * 0 rsv, iov 66 DIVD2 divr.rd, quo.md * * 0 0 rsv, fov, fuv, fdvz 46 DIVF2 divr.rf, quo.mf * * 0 0 rsv, fov, fuv, fdvz 46FD DIVG2 divr.rg, quo.mg * * 0 0 rsv, fov, fuv, fdvz 67 DIVD3 divr.rd, divd.rd, quo.wd * * 0 0 rsv, fov, fuv, fdvz 47 DIVF3 divr.rf, divd.rf, quo.wf * * 0 0 rsv, fov, fuv, fdvz 47FD DIVG3 divr.rg, divd.rg, quo.wg * * 0 0 rsv, fov, fuv, fdvz 74 EMODD mulr.rd, mulrx.rb, muld.rd, int.wl, fract.wd * * * 0 rsv, fov, fuv, iov 54 EMODF mulr.rf, mulrx.rb, muld.rf, int.wl, fract.wf * * * 0 rsv, fov, fuv, iov 54FD EMODG mulr.rg, mulrx.rw, muld.rg, int.wl, fract.wg * * * 0 rsv, fov, fuv, iov 72 MNEGD src.rd, dst.wd * * 0 0 rsv 52 MNEGF src.rf, dst.wf * * 0 0 rsv 52FD MNEGG src.rg, dst.wg * * 0 0 rsv 70 MOVD src.rd, dst.wd * * 0 - rsv 50 MOVF src.rf, dst.wf * * 0 - rsv 50FD MOVG src.rg, dst.wg * * 0 - rsv 64 MULD2 mulr.rd, prod.md * * 0 0 rsv, fov, fuv 44 MULF2 mulr.rf, prod.mf * * 0 0 rsv, fov, fuv 44FD MULG2 mulr.rg, prod.mg * * 0 0 rsv, fov, fuv 65 MULD3 mulr.rd, muld.rd, prod.wd * * 0 0 rsv, fov, fuv 45 MULF3 mulr.rf, muld.rf, prod.wf * * 0 0 rsv, fov, fuv 45FD MULG3 mulr.rg, muld.rg, prod.wg * * 0 0 rsv, fov, fuv 75 POLYD arg.rd, degree.rw, table.ab * * 0 0 rsv, fov, fuv 55 POLYF arg.rf, degree.rw, table.ab * * 0 0 rsv, fov, fuv 55FD POLYG arg.rf, degree.rw, table.ab * * 0 0 rsv, fov, fuv 62 SUBD2 sub.rd, dif.md * * 0 0 rsv, fov, fuv 42 SUBF2 sub.rf, dif.mf * * 0 0 rsv, fov, fuv 42FD SUBG2 sub.rg, dif.mg * * 0 0 rsv, fov, fuv 63 SUBD3 sub.rd, min.rd, dif.wd * * 0 0 rsv, fov, fuv 43 SUBF3 sub.rf, min.rf, dif.wf * * 0 0 rsv, fov, fuv 43FD SUBG3 sub.rg, min.rg, dif.wg * * 0 0 rsv, fov, fuv 73 TSTD src.rd * * 0 0 rsv 53 TSTF src.rf * * 0 0 rsv 53FD TSTG src.rg * * 0 0 rsv CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 26 ARCHITECTURE SUMMARY 2.4.11 Microcode-Assisted Emulated Instructions - The chip provides microcode assistance for the macrocode emulation of these instructions. The chip processes each operand specifier, creates a standard argument list, and invokes an emulation routine to perform emulation. Opcode Instruction N Z V C Exceptions ------ ----------- ------- ---------- 20 ADDP4 addlen.rw, addaddr.ab, sumlen.rw, sumaddr.ab * * * 0 rsv, dov 21 ADDP6 add1len.rw, add1addr.ab, add2len.rw, add2addr.ab, * * * 0 rsv, dov sumlen.rw, sumaddr.ab F8 ASHP cnt.rb, srclen.rw, srcaddr.ab, round.rb, * * * 0 rsv, dov dstlen.rw, dstaddr.ab 35 CMPP3 len.rw, src1addr.ab, src2addr.ab * * 0 0 37 CMPP4 src1len.rw, src1addr.ab, src2len.rw, src2addr.ab * * 0 0 0B CRC tbl.ab, inicrc.rl, strlen.rw, stream.ab * * 0 0 F9 CVTLP src.rl, dstlen.rw, dstaddr.ab * * * 0 rsv, dov 36 CVTPL srclen.rw, srcaddr.ab, dst.wl * * * 0 rsv, iov 08 CVTPS srclen.rw, srcaddr.ab, dstlen.rw, dstaddr.ab * * * 0 rsv, dov 09 CVTSP srclen.rw, srcaddr.ab, dstlen.rw, dstaddr.ab * * * 0 rsv, dov 24 CVTPT srclen.rw, srcaddr.ab, tbladdr.ab, * * * 0 rsv, dov dstlen.rw, dstaddr.ab 26 CVTTP srclen.rw, srcaddr.ab, tbladdr.ab, * * * 0 rsv, dov dstlen.rw, dstaddr.ab 27 DIVP divrlen.rw, divraddr.ab, divdlen.rw, divdaddr.ab, * * * 0 rsv, dov, ddvz quolen.rw, quoaddr.ab 38 EDITPC srclen.rw, srcaddr.ab, pattern.ab, dstaddr.ab * * * * rsv, dov 39 MATCHC objlen.rw, objaddr.ab, srclen.rw, srcaddr.ab 0 * 0 0 34 MOVP len.rw, srcaddr.ab, dstaddr.ab * * 0 0 2E MOVTC srclen.rw, srcaddr.ab, fill.rb, tbladdr.ab, * * 0 * dstlen.rw, dstaddr.ab 2F MOVTUC srclen.rw, srcaddr.ab, esc.rb, tbladdr.ab, * * * * dstlen.rw, dstaddr.ab 25 MULP mulrlen.rw, mulraddr.ab, muldlen.rw, muldaddr.ab, * * * 0 rsv, dov prodlen.rw, prodaddr.ab 22 SUBP4 sublen.rw, subaddr.ab, diflen.rw, difaddr.ab * * * 0 rsv, dov 23 SUBP6 sublen.rw, subaddr.ab, minlen.rw, minaddr.ab, * * * 0 rsv, dov diflen.rw, difaddr.ab CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 27 ARCHITECTURE SUMMARY 2.5 Memory Management The VAX architecture provides a four gigabyte (2**32) virtual address space, divided into two sections, system space and process space. Process space is further subdivided into the P0 region and the P1 region. 2.5.1 Memory Management Control Registers - Memory management is controlled by three processor registers: Memory Management Enable (MAPEN), Translation Buffer Invalidate Single (TBIS), and Translation Buffer Invalidate All (TBIA). MAPEN contains one bit: MAPEN<0> = MME enables memory management. 3 1 1 0 +-------------------------------------------------------------+-+ | |M| | MBZ |M| :MAPEN | |E| +-------------------------------------------------------------+-+ TBIS controls translation buffer invalidation. Writing a virtual address into TBIS invalidates any entry which maps that virtual address. 3 1 0 +---------------------------------------------------------------+ | Virtual Address | :TBIS +---------------------------------------------------------------+ TBIA also controls translation buffer invalidation. Writing a zero into TBIA invalidates the entire translation buffer. 3 1 0 +---------------------------------------------------------------+ | MBZ | :TBIA +---------------------------------------------------------------+ CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 28 ARCHITECTURE SUMMARY 2.5.2 System Space Address Translation - A virtual address with bits <31:30> = 2 is an address in the system virtual address space. System virtual address space is mapped by the System Page Table (SPT), which is defined by the System Base Register (SBR) and the System Length Register (SLR). The SBR contains the physical address of the the System Page Table. The SLR contains the size of the SPT in longwords, that is, the number of Page Table Entries. The Page Table Entry addressed by the System Base Register maps the first page of system virtual address space, that is, virtual byte address 80000000 (hex). 3 3 2 1 0 9 2 1 0 +---+-------------------------------------------------------+---+ |MBZ| physical longword address of SPT |MBZ| :SBR +---+-------------------------------------------------------+---+ 3 2 2 1 2 1 0 +-------------------+-------------------------------------------+ | MBZ | length of SPT in longwords | :SLR +-------------------+-------------------------------------------+ CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 29 ARCHITECTURE SUMMARY 3 3 2 1 0 9 9 8 0 +---+--------------------+--------+ SVA: | 2 | | byte | (System Virtual +---+--------------------+--------+ Address) | extract and | | 3 2|2 check length | | 1 3|2 2|10 | +--------+--------------------+--+ | | 0 | | 0| | +--------+--------------------+--+ | | | add | | +-----------------------------+--+ | SBR: | Physical Base Adr of SPT | 0| | +-----------------------------+--+ | | yields | | +-----------------------------+--+ | | Physical Adr of PTE | 0| | +-----------------------------+--+ | | fetch | | 3 3 2 2 | 1 0 1 0 0 | +-+--------+--------------------+ | PTE: |1| | PFN | | +-+--------+--------------------+ | check access | this access check | | | in current mode | | | | | |2 | | |9 9|8 V 0 +--------------------+--------+ Physical Adr of Data: | | | +--------------------+--------+ System Virtual to Physical Translation CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 30 ARCHITECTURE SUMMARY 2.5.3 Process Space Address Translation - A virtual address with bit <31> = 0 is an address in the process virtual address space. Process space is divided into two equal sized, separately mapped regions. If virtual address bit <30> = 0, the address is in region P0. If virtual address bit <30> = 1, the address is in region P1. 2.5.3.1 P0 Region Address Translation - The P0 region of the address space is mapped by the P0 Page Table (P0PT), which is defined by the P0 Base Register (P0BR) and the P0 Length Register (P0LR). The P0BR contains the system virtual address of the P0 Page Table. The P0LR contains the size of the P0PT in longwords, that is, the number of Page Table Entries. The Page Table Entry addressed by the P0 Base Register maps the first page of the P0 region of the virtual address space, that is, virtual byte address 0. 3 3 2 1 0 9 2 1 0 +---+-------------------------------------------------------+---+ | 2 | system virtual longword address of P0PT |MBZ| :P0BR +---+-------------------------------------------------------+---+ 3 2 2 1 2 1 0 +-------------------+-------------------------------------------+ | MBZ | length of P0PT in longwords | :P0LR +-------------------+-------------------------------------------+ CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 31 ARCHITECTURE SUMMARY 3 3 2 1 0 9 9 8 0 +---+--------------------+--------+ PVA: | 0 | | byte | (Process Virtual +---+--------------------+--------+ Address) | extract and | | 3 2|2 check length | | 1 3|2 2|10 | +--------+--------------------+--+ | | 0 | | 0| | +--------+--------------------+--+ | | | add | | +-----------------------------+--+ | P0BR: | Sys Virt Base Adr of P0PT | 0| | +-----------------------------+--+ | | yields | | +-----------------------------+--+ | | Virtual Adr of PTE | 0| | +-----------------------------+--+ | | fetch by system space | translation algorithm, | including length check | | 3 3 2 2 | 1 0 1 0 0 | +-+--------+--------------------+ | PTE: |1| | PFN | | +-+--------+--------------------+ | check access | this access check | | | in current mode | | | | | |2 | | |9 9|8 V 0 +--------------------+--------+ Physical Adr of Data: | | | +--------------------+--------+ P0 Virtual to Physical Translation CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 32 ARCHITECTURE SUMMARY 2.5.3.2 P1 Region Address Translation - The P1 region of the address space is mapped by the P1 Page Table (P1PT), which is defined by the P1 Base Register (P1BR) and the P1 Length Register (P1LR). Because P1 space grows towards smaller addresses, and because a consistent hardware interpretation of the base and length registers is desirable, P1BR and P1LR describe the portion of P1 space that is NOT accessible. Note that P1LR contains the number of nonexistent PTEs. P1BR contains the virtual address of what would be the PTE for the first page of P1, that is, virtual byte address 40000000 (hex). The address in P1BR is not necessarily a valid virtual address, but all the addresses of PTEs must be valid virtual addresses. 3 1 2 1 0 +-----------------------------------------------------------+---+ | virtual longword address of P1PT |MBZ| :P1BR +-----------------------------------------------------------+---+ 3 2 2 1 2 1 0 +-------------------+-------------------------------------------+ | MBZ | length of P1PT in longwords | :P1LR +-------------------+-------------------------------------------+ CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 33 ARCHITECTURE SUMMARY 3 3 2 1 0 9 9 8 0 +---+--------------------+--------+ PVA: | 1 | | byte | (Process Virtual +---+--------------------+--------+ Address) | extract and | | 3 2|2 check length | | 1 3|2 2|10 | +--------+--------------------+--+ | | 0 | | 0| | +--------+--------------------+--+ | | add | | +-----------------------------+--+ | P1BR: | Virt Base Adr of P1PT | 0| | +-----------------------------+--+ | | yields | | +-----------------------------+--+ | | Virtual Adr of PTE | 0| | +-----------------------------+--+ | | fetch by system space | translation algorithm, | including length check | | 3 3 2 2 | 1 0 1 0 0 | +-+--------+--------------------+ | PTE: |1| | PFN | | +-+--------+--------------------+ | check access | this access check | | | in current mode | | | | | |2 | | |9 9|8 V 0 +--------------------+--------+ Physical Adr of Data: | | | +--------------------+--------+ P1 Virtual to Physical Translation CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 34 ARCHITECTURE SUMMARY 2.5.4 Page Table Entry - The format of a page table entry is: 3 3 2 2 2 2 2 2 2 2 1 0 7 6 5 4 3 2 1 0 0 +-+-------+-+-+---+---+-----------------------------------------+ |V| PROT |M|0|OWN| 0 | PFN | :PTE +-+-------+-+-+---+---+-----------------------------------------+ The protection code access matrix is: code current mode decimal binary mnemonic K E S U comment ------- ------ -------- - - - - ------- 0 0000 NA - - - - no access 1 0001 unpredictable reserved 2 0010 KW RW - - - 3 0011 KR R - - - 4 0100 UW RW RW RW RW all access 5 0101 EW RW RW - - 6 0110 ERKW RW R - - 7 0111 ER R R - - 8 1000 SW RW RW RW - 9 1001 SREW RW RW R - 10 1010 SRKW RW R R - 11 1011 SR R R R - 12 1100 URSW RW RW RW R 13 1101 UREW RW RW R R 14 1110 URKW RW R R R 15 1111 UR R R R R K = kernel R = read E = executive W = write S = supervisor - = no access U = user CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 35 ARCHITECTURE SUMMARY 2.5.5 Translation Buffer - In order to save actual memory references when repeatedly referencing pages, The CVAX CPU chip uses a translation buffer to remember successful virtual address translations and page status. The translation buffer contains 28 fully associative entries. Both system and process references share these entries. Translation buffer entries are replaced using a not last used (NLU) algorithm. NLU guarantees that the replacement pointer is not pointing at the last translation buffer entry to be used. This is accomplished by rotating the replacement pointer to the next sequential translation buffer entry if it is pointing to an entry that has just been accessed. Both D-stream and I-stream references can cause the NLU to cycle. When the translation buffer does not contain a reference's virtual address and page status, the machine updates the translation buffer by replacing the entry that is selected by the replacement pointer. CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 36 ARCHITECTURE SUMMARY 2.6 Exceptions And Interrupts Both exceptions and interrupts divert execution from the normal flow of control. An exception is caused by the execution of the current instruction, while an interrupt is caused by some activity outside the central processor. 2.6.1 Interrupts - The VAX architecture has 31 interrupt priority levels (IPL), used as follows: IPL levels interrupt condition ---------- ------------------- 1F unused 1E PWRFL L asserted 1D MEMERR L asserted 1B - 1C unused 1A CRD L asserted 18 - 19 unused 17 IRQ<3> L asserted 16 IRQ<2> L asserted 16 INTTIM L asserted 15 IRQ<1> L asserted 14 IRQ<0> L asserted 10 - 13 unused 01 - 0F software interrupt request The interrupt system is controlled by the Interrupt Priority Level Register (IPL, corresponds to PSL<20:16>), the Software Interrupt Request Register (SIRR), and the Software Interrupt Summary Register (SISR). 3 1 5 4 0 +----------------------------------------------------+----------+ | ignored, returns 0 |PSL<20:16>| :IPL +----------------------------------------------------+----------+ 3 1 4 3 0 +-------------------------------------------------------+-------+ | ignored |request| :SIRR +-------------------------------------------------------+-------+ 3 1 1 1 6 5 0 +-------------------------------+-----------------------------+-+ | | Pending Software Interrupts |M| | | |B| :SISR | |F E D C B A 9 8 7 6 5 4 3 2 1|Z| +-------------------------------+-----------------------------+-+ CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 37 ARCHITECTURE SUMMARY 2.6.2 Exceptions - The VAX architecture recognizes six classes of exceptions. exception class instances --------------- --------- arithmetic traps/faults integer overflow trap integer divide by zero trap subscript range trap floating overflow fault floating divide by zero fault floating underflow fault memory management exceptions access control violation fault translation not valid fault operand reference exceptions reserved addressing mode fault reserved operand fault or abort instruction execution exceptions reserved/privileged instruction fault emulated instruction fault customer reserved instruction fault breakpoint fault ---------------------------------------------------------------- tracing exception trace fault system failure exceptions machine check abort (including read/write bus and parity errors, cache parity errors, and CFPA protocol errors) kernel stack not valid abort interrupt stack not valid abort CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 38 ARCHITECTURE SUMMARY 2.6.3 System Control Block (SCB) - The System Control Block (SCB) is a page aligned table containing the vectors for servicing interrupts and exceptions. The SCB is pointed to by the System Control Block Base Register (SCBB). 3 3 2 1 0 9 9 8 0 +---+-----------------------------------------+-----------------+ |MBZ| physical longword address of SCB | MBZ | :SCBB +---+-----------------------------------------------------------+ The System Control Block format: vector name type #param notes ------ ---- ---- ------ ----- 00 passive release interrupt 0 not generated by the CVAX CPU chip 04 machine check abort 4 parameters depend upon error type 08 kernel stack not valid abort 0 must be serviced on interrupt stack 0C power fail interrupt 0 IPL is raised to 1E 10 reserved/privileged fault 0 instruction 14 customer reserved instruction fault 0 XFC instruction 18 reserved operand fault/ 0 not always recoverable abort 1C reserved addressing mode fault 0 20 access control violation fault 2 parameters are virtual address, status code 24 translation not valid fault 2 parameters are virtual address, status code 28 trace pending (TP) fault 0 2C breakpoint instruction fault 0 30 unused - - compatibility mode in VAX 34 arithmetic trap/ 1 parameter is type code fault 38-3C unused - - - 40 CHMK trap 1 parameter is sign-extended operand word 44 CHME trap 1 parameter is sign-extended operand word CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 39 ARCHITECTURE SUMMARY 48 CHMS trap 1 parameter is sign-extended operand word 4C CHMU trap 1 parameter is sign-extended operand word 50 unused - - - 54 corrected read data interrupt 0 IPL is 1A (CRD L) 58-5C unused - - - 60 memory error interrupt 0 IPL is 1D (MEMERR L) 64-80 unused - - - 84 software level 1 interrupt 0 88 software level 2 interrupt 0 ordinarily used for AST delivery 8C software level 3 interrupt 0 ordinarily used for process scheduling 90-BC software levels 4-15 interrupt 0 C0 interval timer interrupt 0 IPL is 16 (INTTIM L) C4 unused - - - C8 emulation start fault 10 same mode exception, FPD = 0: parameters are opcode, PC, specifiers CC emulation continue fault 0 same mode exception, FPD = 1: no parameters D0-FC unused - - - 100-1FC adapter vectors interrupt 0 200-FFFC device vectors interrupt 0 Vectors in the range of 100-FFFC are used to directly vector interrupts from the external bus. The SCBB vector index is determined from bits <15:2> of the value supplied by external hardware. The new PSL priority level is determined by either the external interrupt request level that caused the interrupt or by bit <0> of the value supplied by external hardware. If bit<0> is 0, the new IPL level is determined by the interrupt request level being serviced. IRQ<3> sets the IPL to 17 (hex); IRQ<2>, 16 (hex); IRQ<1>, 15 (hex); and IRQ<0>, 14 (hex). If bit<0> of the value supplied by external hardware is 1, then the new IPL is forced to 17 (hex). The ability to force the IPL to 17 (hex) supports an external bus, such as the Q-Bus, that can not guarantee that the device generating the SCBB vector index is the device that originally requested the interrupt. For example, the Q-Bus has four separate interrupt request signals that correspond to IRQ<3:0> but only one signal to daisy chain the interrupt grant. Furthermore, devices on the Q-Bus are ordered so that higher priority devices are electrically closer CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 40 ARCHITECTURE SUMMARY to the bus master. If an IRQ<1> is being serviced, there is no guarantee that a higher priority device will not intercept the grant. Software must determine the level of the device that was serviced and set the IPL to the correct value. Only device vectors in the range of 100 to FFFC (hex) should be used, except by devices emulating console storage and terminal hardware. CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 41 ARCHITECTURE SUMMARY 2.6.4 Machine Check Parameters - A machine check occurs as a result of a serious microcode and hardware error conditions including memory subsystem errors. These conditions are: - CFPA protocol error - Impossible situations in memory management - Unused IPL requests - Impossible situations in the microcode - Bus (memory) errors - Multiple errors 2.6.4.1 Types Of Errors - 2.6.4.1.1 CFPA Protocol Error - The CFPA checks for proper ordering of requests from the CPU. If the CFPA detects a protocol violation, a machine check occurs. param meaning ----- ------- 1 CFPA protocol error 2 CFPA reserved instruction 3 CFPA unknown error 4 CFPA unknown error All CFPA protocol error machine checks are NON-RECOVERABLE. The error should be logged, and the currently running process (or the operating system) terminated. 2.6.4.1.2 Impossible Situations In Memory Management - The CVAX CPU does some checking for impossible conditions in the memory management microflows. If an impossible situation is detected, a machine check occurs. param meaning ----- ------- 5 The calculated virtual address for a Process PTE is in P0 space (TB miss flows) 6 The calculated virtual address for a Process PTE is in P1 space (TB miss flows) CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 42 ARCHITECTURE SUMMARY 7 The calculated virtual address for a Process PTE is in P0 space (M = 0 flows) 8 The calculated virtual address for a Process PTE is in P1 space (M = 0 flows) All impossible memory management machine checks are NON-RECOVERABLE. The error should be logged, and the currently running process (or the operating system) terminated. The current memory management registers (P0BR, P1BR, SBR, P0LR, P1LR, SLR) should also be logged. 2.6.4.1.3 Unused IPL Request - The CVAX CPU uses 13 of the 16 hardware interrupt priority levels (IPLs) defined in the VAX architecture. If the interrupt controller requests an interrupt at an unused hardware IPL, a machine check occurs. param meaning ----- ------- 9 The interrupt controller returned an interrupting IPL of 18, 19, or 1B The unused IPL machine check is NON-RECOVERABLE. The error should be logged. A non-vectored interrupt representing a serious error (corrected read data, memory error, power fail, or processor halt) has probably been lost. The operating system should be terminated. 2.6.4.1.4 Impossible Situations In The Microcode - Due to size constraints, erroneous branches in the microcode will usually result in the execution of random microinstruction. However, a few cases are trapped out. If the microcode detects an impossible situation, a machine check occurs. param meaning ----- ------- A MOVC3 or MOVC5 in impossible state (not move forward, move backward, or fill) The impossible microcode machine check is NON-RECOVERABLE. The error should be logged, and the currently running process (or the operating system) terminated. 2.6.4.1.5 Bus (Memory) Errors - If external logic asserts ERR L in response to any memory cycle other than an instruction prefetch or interrupt acknowledge, a CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 43 ARCHITECTURE SUMMARY machine check occurs. param meaning ----- ------- 80 read bus error, normal read 81 read bus error, SPTE, PCB, or SCB read 82 write bus error, normal write 83 write bus error, SPTE or PCB write The bus (memory) error machine checks MAY be recoverable, depending on the error code, the VAX CANT RESTART, and FPD flags in the machine check stack frame, as shown in the following table: error VAX CANT RESTART FPD action --------+-------------------------------+-------------- 80,81 | 0 X | restartable | 1 0 | non-recoverable | 1 1 | restartable | | 82,83 | X X | non-recoverable In addition, bus (memory) error machine checks that are restartable from the chip's point of view may be non-recoverable for system reasons (eg, a read lock may be outstanding). CONSULT THE VARIOUS SYSTEM SPECIFICATIONS FOR FURTHER DETAILS. On a non-recoverable error, the error should be logged, and the currently running process (or the operating system) should be terminated. 2.6.4.1.6 Multiple Errors - If the CVAX CPU encounters nested serious errors (e.g., kernel stack not valid inside a machine check), or other conditions which cannot be processed by macrocode (e.g., HALT instruction in kernel mode), the microcode places the current PC in IPR[SAVEPC], the current PSL, MAPEN, and a restart code in IPR[SAVEPSL], and executes a processor restart. CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 44 ARCHITECTURE SUMMARY 2.6.4.2 Machine Check Processing - The microcode process for machine check is the same for all cases. If any exception is in progress, a processor restart occurs. Otherwise, the current instruction is packed up (MOVC3, MOVC5, POLYf) or unwound. The microcode sets the serious error flag and performs machine check exception processing through SCB vector 4. Note that the exception is always processed on the interrupt stack. The following parameters are pushed on the stack: +-------------------------------------------------------+ | byte count (00000010 hex) | :SP +-------------------------------------------------------+ | machine check code | +-------------------------------------------------------+ | most recent memory address | +-------------------------------------------------------+ | internal state information 1 | +-------------------------------------------------------+ | internal state information 2 | +-------------------------------------------------------+ | PC | +-------------------------------------------------------+ | PSL | +-------------------------------------------------------+ The parameters are: machine check code (hex): 1 = CFPA protocol error 2 = CFPA reserved instruction 3 = CFPA unknown error 4 = CFPA unknown error 5 = process PTE in P0 space (TB miss) 6 = process PTE in P1 space (TB miss) 7 = process PTE in P0 space (M = 0) 8 = process PTE in P1 space (M = 0) 9 = undefined interrupt ID code A = impossible microcode state (MOVCx) 80 = read bus error, normal read 81 = read bus error, SPTE, PCB, or SCB read 82 = write bus error, normal write 83 = write bus error, SPTE or PCB write most recent memory address: <31:0> = current contents of VAP register internal state information 1: <31:24> = current contents of OPCODE<7:0> <23:20> = 1110 <19:16> = current contents of HSIR<3:0> <15:8> = current contents of CADR<7:0> CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 45 ARCHITECTURE SUMMARY <7:0> = current contents of MSER<7:0> internal state information 2: <31:24> = current contents of SC<7:0> <23:22> = 11 <21:16> = current contents of STATE<5:0> <15> = current contents of VAX CANT RESTART bit <14:12> = 111 <11:8> = current ALU condition codes <7:0> = delta PC at time of exception PC: <31:0> = PC of start of current instruction PSL: <31:0> = current contents of PSL When exception processing is complete, the serious error flag is cleared, and the next instruction is decoded. 2.6.4.3 Processor Restart - If the hardware or kernel software environment becomes severely corrupted, the chip may be unable to continue normal processing. In these instances, the chip executes a processor restart and passes control to recovery code beginning at physical address 20040000 (hex). IPR[SAVEPC] contains the previous PC, IPR[SAVEPSL] contains the previous PSL with MAPEN in bit<15>, a valid stack flag in bit<14>, and a restart code in bits <13:8>. The restart codes are as follows: code condition ---- --------- 2 HALT L asserted 3 initial power on 4 interrupt stack not valid during exception 5 machine check during normal exception 6 HALT instruction executed in kernel mode 7 SCB vector bits<1:0> = 11 8 SCB vector bits<1:0> = 10 A CHMx executed while on interrupt stack 10 ACV or TNV during machine check exception 11 ACV or TNV during kernel stack not valid exception 12 machine check during machine check exception 13 machine check during kernel stack not valid exception 19 PSL<26:24> = 101 during interrupt or exception 1A PSL<26:24> = 110 during interrupt or exception 1B PSL<26:24> = 111 during interrupt or exception 1D PSL<26:24> = 101 during REI 1E PSL<26:24> = 110 during REI 1F PSL<26:24> = 111 during REI A processor restart sets the state of the chip as follows: IPR[SAVEPC] = saved PC CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 46 ARCHITECTURE SUMMARY IPR[SAVEPSL] = saved PSL<31:16,7:0> in <31:16,7:0> saved MAPEN<0> in <15> valid stack flag in <14> saved restart code in <13:8> SP = interrupt stack pointer PSL = 041F0000 (hex) PC = 20040000 (hex) MAPEN = 0 SISR = 0 (powerup only) ASTLVL = 4 (powerup only) ICCS = 0 (powerup only) MSER = 0 (powerup only) CADR = 0 (powerup only) all else = undefined CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 47 ARCHITECTURE SUMMARY 2.7 Process Structure A process is a single thread of execution. The context of the current process is contained in the Process Control Block (PCB). The PCB is pointed to by the Process Control Block Base register (PCBB). 3 3 2 1 0 9 2 1 0 +---+-------------------------------------------------------+---+ |MBZ| physical longword address of PCB |MBZ| :PCBB +---+-------------------------------------------------------+---+ CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 48 ARCHITECTURE SUMMARY 2.7.1 Process Control Block (PCB) - 3 1 0 +---------------------------------------------------------------+ | KSP | :PCB +---------------------------------------------------------------+ | ESP | +4 +---------------------------------------------------------------+ | SSP | +8 +---------------------------------------------------------------+ | USP | +12 +---------------------------------------------------------------+ | R0 | +16 +---------------------------------------------------------------+ | R1 | +20 +---------------------------------------------------------------+ | R2 | +24 +---------------------------------------------------------------+ | R3 | +28 +---------------------------------------------------------------+ | R4 | +32 +---------------------------------------------------------------+ | R5 | +36 +---------------------------------------------------------------+ | R6 | +40 +---------------------------------------------------------------+ | R7 | +44 +---------------------------------------------------------------+ | R8 | +48 +---------------------------------------------------------------+ | R9 | +52 +---------------------------------------------------------------+ | R10 | +56 +---------------------------------------------------------------+ | R11 | +60 +---------------------------------------------------------------+ | AP(R12) | +64 +---------------------------------------------------------------+ | FP(R13) | +68 +---------------------------------------------------------------+ | PC | +72 +---------------------------------------------------------------+ | PSL | +76 +---------------------------------------------------------------+ | P0BR | +80 +---------+-----+---+-------------------------------------------+ | | AST | | | +84 | MBZ | LVL |MBZ| P0LR | +---------+-----+---+-------------------------------------------+ | P1BR | +88 +-+-----------------+-------------------------------------------+ |P| | | +92 |M| MBZ | P1LR | |E| | | +-+-------------------------------------------------------------+ CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 49 ARCHITECTURE SUMMARY Note: The PME field is unused. CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 50 ARCHITECTURE SUMMARY 2.8 Processor Registers Each of the processor registers listed in the table below falls into one of the following categories: 1 = implemented by the CVAX CPU Chip as specified in the VAX Architecture Standard (DEC Standard 032) 2 = implemented by the CVAX CPU Chip uniquely 3 = passed to external logic via an external processor register cycle; if not implemented externally, read as zero, nopped on write 4 = access not allowed (reserved operand fault) The column labeled "INIT?" means is this register initialized in the CVAX on chip power-up microcode. YES = it is initialized by power-up code NO = it is NOT initialized by power-up code but IS valid --- = register contents are undefined after power-up Number Register Name Mnemonic Type Scope Init? Category ------ ------------- -------- ---- ----- ----- -------- 0 Kernel Stack Pointer KSP rw proc -- 1 1 Executive Stack Pointer ESP rw proc -- 1 2 Supervisor Stack Pointer SSP rw proc -- 1 3 User Stack Pointer USP rw proc -- 1 4 Interrupt Stack Pointer ISP rw cpu -- 1 5 not implemented -- -- -- -- 3 6 not implemented -- -- -- -- 3 7 not implemented -- -- -- -- 3 8 P0 Base Register P0BR rw proc -- 1 9 P0 Length Register P0LR rw proc -- 1 10 P1 Base Register P1BR rw proc -- 1 11 P1 Length Register P1LR rw proc -- 1 12 System Base Register SBR rw cpu -- 1 13 System Length Register SLR rw cpu -- 1 14 not implemented -- -- -- -- 3 15 not implemented -- -- -- -- 3 16 Process Control Block Base PCBB rw proc -- 1 17 System Control Block Base SCBB rw cpu -- 1 18 Interrupt Priority Level IPL rw cpu yes 1 19 AST Level ASTLVL rw proc yes 1 20 Software Interrupt Request SIRR w cpu -- 1 21 Software Interrupt Summary SISR rw cpu yes 1 22 not implemented -- -- -- -- 3 23 not implemented -- -- -- -- 3 24 Interval Clock Control ICCS rw cpu yes 2 25 not implemented -- -- -- -- 3 26 not implemented -- -- -- -- 3 27 not implemented -- -- -- -- 3 28 not implemented -- -- -- -- 3 29 not implemented -- -- -- -- 3 CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 51 ARCHITECTURE SUMMARY 30 not implemented -- -- -- -- 3 31 not implemented -- -- -- -- 3 32 not implemented -- -- -- -- 3 33 not implemented -- -- -- -- 3 34 not implemented -- -- -- -- 3 35 not implemented -- -- -- -- 3 36 not implemented -- -- -- -- 3 37 Cache Disable CADR rw cpu yes 2 38 not implemented -- -- -- -- 3 39 Memory System Error MSER rw cpu yes 2 40 not implemented -- -- -- -- 3 41 not implemented -- -- -- -- 3 42 Console Saved PC SAVPC r cpu -- 2 43 Console Saved PSL SAVPSL r cpu -- 2 44 not implemented -- -- -- -- 3 45 not implemented -- -- -- -- 3 46 not implemented -- -- -- -- 3 47 not implemented -- -- -- -- 3 48 not implemented -- -- -- -- 3 49 not implemented -- -- -- -- 3 50 not implemented -- -- -- -- 3 51 not implemented -- -- -- -- 3 52 not implemented -- -- -- -- 3 53 not implemented -- -- -- -- 3 54 not implemented -- -- -- -- 3 55 not implemented -- -- -- -- 3 56 Memory Management Enable MAPEN rw cpu yes 1 57 Trans. Buf. Invalidate All TBIA w cpu -- 1 58 Trans. Buf. Invalidate Single TBIS w cpu -- 1 59 not implemented -- -- -- -- 3 60 not implemented -- -- -- -- 3 61 not implemented -- -- -- -- 3 62 System Identification SID r cpu no 1 63 Translation Buffer Check TBCHK w cpu -- 1 64:127 reserved -- -- -- -- 4 The implementation specific processor registers are described below. 2.8.1 Interval Clock Control And Status Register (ICCS) - The ICCS register controls the interval timer (INTTIM L) interrupt. It is similar to the ICCS register described in the VAX Architecture Specification but contains only a single bit to enable or disable the interval timer interrupt: CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 52 ARCHITECTURE SUMMARY 3 1 7 6 5 0 +------------------------------------------------+-+------------+ | |I| | | |E| | : ICCS +------------------------------------------------+-+------------+ Bit <6> is read/write. When set, interval timer interrupts are enabled at IPL16; when clear, interval timer interrupts are disabled. Bits <31:7,5:0> read as zero and are ignored on writes. Bit <6> is cleared in the restart process. 2.8.2 Cache Disable Register (CADR) - 3 1 8 7 6 5 4 3 2 1 0 +----------------------------------------------+---+---+-+-+-+-+ | |SEN|CEN| | |W|D| | 0 | | |1|1|W|I| : CADR | | | | | | |A| +----------------------------------------------+---+---+-+-+-+-+ CADR <31:8> always read as 0's. CADR<3:2> always reads as 11. CADR <7:4,1:0> initialize to 0 when RESET L is asserted. If CADR<0> is 0, the cache is flushed (all valid bits set to invalid state) whenever the CADR is written. Writing the CADR will not flush the cache if CADR<0> is 1. CADR <7:6> (Set Enable) are read/write and are encoded as follows: <7:6> Set 2 Set 1 ----- ----- ----- 00 disabled disabled 01 disabled enabled 10 enabled disabled 11 enabled enabled CADR <5:4> (Cache Enable) are read/write and are encoded as follows: <5:4> Action ----- ------ 00 Cache disabled 01 D-stream only stored in cache (diagnostic use) 10 I-stream only stored in cache 11 I-stream and D-stream stored in cache When CADR <5:4> = 10 (I-stream only stored in cache), the CVAX CPU chip automatically flushes the cache whenever an REI instruction is executed. The VAX SRM states that an REI instruction must be executed prior to running code out of an updated page of memory. Therefore, systems that follow the SRM CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 53 ARCHITECTURE SUMMARY need not monitor DMA writes in order to prevent stale data from accumulating in the cache. When CADR<5:4> = 11 or 01, invalidate-on-hit cycles must be used to remove stale data from the cache. CADR <1> (Write Wrong Parity) is read/write. When set, incorrect parity is stored in the cache whenever the cache is written. CADR <0> (Diagnostic mode) is read/write. When set, all quadword write references write through the cache irrespective of hit/miss or bus error status. In addition, no bus error induced machine check abort is generated during a bus write. When cleared, a normal non-allocating cache write through operation occurs during write cycles. Diagnostic mode does not effect read operations. Note that diagnostic mode blocks the flush of the cache when the CADR is written. There are several restrictions on the way Diagnostic mode can be used. 1. Diagnostic mode should only be selected when one set is enabled. 2. The exact diagnostic allocation mechanism is very esoteric. A validate write allocation will occur only if a specific sequence of instructions is followed. The first instruction must be a quadword write (MOVQ) to a quadword aligned destination. This instruction writes the second longword of the source operand to the first longword of the cache entry selected by the destination address. The first longword of the source is not used and the second longword of the cache entry remains unchanged. In addition, the cache tag and valid bits are set so that subsequent reads and writes to either longword in the destination will report a cache hit. 3. The second instruction must be a cacheable read operation. 4. The third instruction must be a longword write to the address corresponding to the second longword in the cache entry. A macrocode listing illustrating this sequence is shown below: . . . MOVQ #quadsrc, @#quaddst ; writes longword quadsrc+4 into longword quaddst MOVL #quaddst, R0 ; reads allocated longword quaddst MFPR #mser, R1 ; get MSER in order to look at H/M bit later MOVL #longsrc, @#(quaddst+4) ; writes 2nd longword quaddst+4 . . . When this sequence is followed, each cache entry can be allocated with any arbitrary address. CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 54 ARCHITECTURE SUMMARY 2.8.3 Memory System Error Register (MSER) - 3 1 8 7 6 5 4 3 2 1 0 +----------------------------------------------+-+-+-+-+-+-+-+-+ | |H|D|M|M| | |D|T| | 0 |M|A|C|C|0|0|A|A| : MSER | | |L|D|C| | |T|G| +----------------------------------------------+-+-+-+-+-+-+-+-+ MSER <31:8> always read as 0's. MSER<3:2> always read as 0's. MSER <6:4,1:0> are read/write and initialize to 0's when RESET L is asserted. MSER <7> is read-only and initializes to 0 when RESET L is asserted. MSER<6:4,1:0> are cleared whenever it is written (MTPR MSER), irrespective of the write data. MSER <7> (hit/miss) is updated only on references that can be potentially stored in the cache. This excludes all I/O space references; if CADR <5> = 0, all memory space instruction stream references; if CADR <4> = 0, all memory space data stream references; and all read lock references. On all references that qualify, MSER <7> is cleared if the reference is stored in the cache and set if it is not stored in the cache. MSER<6> (DAL parity error) is set whenever a DAL parity error is detected on either a demand or request read cycle. MSER <5> (machine check abort - DAL parity error) is set whenever a machine check is caused by a DAL parity error. A DAL parity error will only cause a machine check on a demand read cycle. MSER <4> (machine check abort - cache parity error) is set whenever a machine check is caused by a cache parity error (tag or data). A cache parity error will only cause a machine check on a demand read cycle. MSER<1:0> are independently set to show the scope of a cache parity error on either a demand or request cycle. MSER<0> is set to indicate that the cache parity error was caused by a tag error; MSER<1>, by a data error. Note that a simultaneous cache tag and data parity error will only log the fact that a cache tag parity error occurred. MSER <6:4,1:0> are sticky in the sense that once set, they remain set until MSER is explicitly cleared by writing the MSER (MTPR MSER irrespective of the data). Parity errors occurring while an error condition is posted in MSER can only set additional bit, i.e., MSER<6:4,1:0> cannot be cleared on subsequent errors. 2.8.4 Console Saved Registers (SAVPC, SAVPSL) - The console saved registers (SAVPC, SAVPSL) record the value of CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 55 ARCHITECTURE SUMMARY the PC and PSL, respectively, at the time a chip restart occurs. See the section on Restarts, above, for details. 2.8.5 System Identification Register (SID) - The SID is a read only constant register that specifies the processor type as a CVAX CPU (SID<31:24>=10 decimal). The SID<7:0> reflects the microcode revision level. 3 2 2 1 4 3 8 7 0 +----------------+-----------------------------+---------------+ | | | | | 10 (decimal) | RESERVED | Microcode Rev.| | | | | +----------------+-----------------------------+---------------+ CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 56 INTERNAL CACHE 3 INTERNAL CACHE The CVAX CPU chip contains a 1Kb, two-way associative, 8 byte block size cache: 3 3 2 Bytes/row 2 Bytes/row +------------------------+ +------------------------+ | | | | | | | | | | | | 6 | Set 1 | | Set 2 | 2 Row | | | | | | | | | | | | | | | | +------------------------+ +------------------------+ 93 0 93 0 1 6 3 Total storage = 2 sets * 2 rows * 2 bytes per row = 1024 bytes Each physical address is logically subdivided as follows: 29 28 9 8 3 2 0 +--+----------------------------------------------+-------+----+ | | | | | | | Label | | | | | | | | +--+----------------------------------------------+-------+----+ | | | +-- I/O space | | cache index-------+ | | byte/word/longword select-+ CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 57 INTERNAL CACHE When bit <29> is set, I/O space is referenced. No I/O space reference is ever stored in the cache. When the reference is in memory space, bits <8:3> access an entry in each set of the cache. Each entry contains tag and data information and is organized as follows: 19 0 +---+---+----------------------------------------------+ | | | | | P | V | Tag | | | | | +---+---+----------------------------------------------+ | | | +--- Valid | +------- Parity 63 56 55 48 47 40 39 32 31 24 23 16 15 8 7 0 +-+------+-+------+-+------+-+------+-+------+-+------+-+------+-+------+ | | | | | | | | | | | | | | | | | | | B7 | | B6 | | B5 | | B4 | | B3 | | B2 | | B1 | | B0 | | | | | | | | | | | | | | | | | | +-+------+-+------+-+------+-+------+-+------+-+------+-+------+-+------+ | | | | | | | | +-Parity +-Parity +-Parity +-Parity +-Parity +-Parity +-Parity +-Parity A memory reference is stored in the cache when all of the following conditions are met: 1. The physical address label field exactly equals the cache tag field. 2. The cache tag valid bit is set. 3. No parity errors exist in the tag field. 4. No parity errors exist in the four bytes selected by bit <2> of the physical address, i.e., B3-B0 if B<2>=0; B7-B4 if B<2>=1. 3.1 Cache Allocation A cache block (8 bytes) is allocated whenever a read reference that can be potentially stored in the cache is not stored in the cache. This excludes all I/O space references; if CADR <5> = 0, all memory space instruction stream references; if CADR <4> = 0, all memory space data stream references; and all read lock references. Random set selection is used. External logic can determine which set is being selected by monitoring the CS/DP<3> pin. All cacheable read references initiate quadword read cycles. CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 58 INTERNAL CACHE 3.2 Read Cycle Classification The CVAX CPU chip classifies read cycles into three groups: request I-stream reads; request D-stream reads; and demand D-stream reads. In general, request reads are generated whenever the data is not immediately needed by the chip. Specifically, prefetching the I-stream (request I-stream) and filling the second cache longword during a D-stream read (request D-stream) generate request reads. A D-stream demand read is generated whenever data is immediately needed by the chip. Specifically, operand, PTE, SCB, and PCB references all generate D-stream demand cycles. Demand and request reads differ in the way they respond to errors reported during the reference. In general, request read errors do not affect program flow whereas demand read errors cause a machine check abort. The following tables highlight the effects various errors have during demand and request cycles. Bus Error effect (including DAL parity errors) ---------------------------------------------- Prefetcher Cache Error Status Machine flows ---------- ------ ------------ ------------- Demand entry is logged in machine check D-stream - invalidated** MSER<6:5>* abort (read) Write - - - machine check abort Request - entry is logged in - D-stream invalidated** MSER<6>* (read) Request prefetching entry is logged in - I-stream halted invalidated** MSER<6>* (read) * only DAL parity errors log status ** the entire cache row selected by the faulting address is invalidated irrespective of whether the reference is cacheable, i.e., the entries from both sets are invalidated. CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 59 INTERNAL CACHE Cache Parity Error effect ------------------------- Prefetcher Cache Error Status Machine flows ---------- ------ ------------ ------------- Demand flush cache**** logged in machine check D-stream - disable caching MSER<4:0> abort (read) Write - flush cache**** logged in - cache hit MSER<3:0>*** Write n o t p o s s i b l e cache miss Request n o t p o s s i b l e D-stream (read) Request prefetching flush cache**** logged in - I-stream halted MSER<3:0> (read) *** parity error is detected only in tags **** the cache is flushed only if CADR<0> is cleared. The cache is never flushed if CADR<0> is set. Memory Management Error effect ------------------------------ Prefetcher Machine flows ---------- ------------- Demand memory management D-stream - fault (ACV,TNV,etc.) (read) Write - memory management fault (ACV,TNV,etc.) Request n o t p o s s i b l e D-stream (read) Request prefetching I-stream halted - (read) - = not effected The demand D-stream references are further classified as read lock; read no modify intent; and read modify intent. Classification information is passes to external logic on the CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 60 INTERNAL CACHE CS/DP<2:0> L pins. 3.3 Cache Parity The CVAX CPU chip protects the internal cache with parity. Each eight bit byte of cache data and the twenty bit tag field is checked by a parity bit. Odd data bytes store odd parity; even data bytes, even parity. The tag field stores odd parity. The stored parity is valid only when the valid bit associated with the cache entry is set. Cache parity is checked on all cacheable read and write references and DMA invalidate cycles. Read cycles report cache parity errors when a valid tag matches bits <28:9> of the physical address, and either the stored tag or the longword selected by address bit <2> generate a parity error. Write and DMA invalidate cycles report cache parity errors when a valid tag matches bits <28:9> of the physical address, and the stored tag generates an error. The action following the detection of a cache parity error depends on the reference type: during a demand D-stream reference, the entire cache is flushed, the cache is turned off (CADR is cleared), the cause of the error is logged in MSER<4:0>, and a machine check abort is initiated. During a request I-stream reference, the entire cache is flushed, the cause of the error is logged in MSER<3:0>, prefetching is halted, no abort occurs, and the cache remains enabled. During a DMA invalidate cycle, no abort occurs, the cache remain unchanged, and the error is logged in MSER<0>. 3.4 DAL H Parity The CVAX CPU chip protects DAL data with parity. Each eight bit DAL byte is conditionally checked by a parity bit. Odd data bytes show odd parity; even data bytes, even parity. The parity sense is alternated in order to catch both stuck at one and stuck at zero faults. DAL H parity checking can be disable, reference by reference, by negating the external pin DPE L. The action following the detection of a DAL H parity error depends on the reference type: during a demand D-stream reference, the cache entry is invalidated, the cause of the error is logged in MSER<6:5>, and a machine check abort is initiated. During request D-stream and I-stream references, the cache entry is invalidated, the cause of the error is logged in MSER<6>, but no abort occurs. CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 61 INTERFACE 4 INTERFACE This section details the pin assignments for the CVAX CPU chip. 4.1 Pinouts 4.1.1 Summary - The CVAX CPU chip has the following pin assignments: Signals Signal Type Number of Pins Running Total ------- ----------- -------------- ------------- Data and Address I/O 32 32 Cycle status/parity I/O 4 36 Data parity enable I/O 1 37 Address strobe I/O 1 38 Data strobe O 1 39 Byte mask O 4 43 Write O 1 44 Data buffer enable O 1 45 Ready I 1 46 Error I 1 47 Reset I 1 48 Halt I 1 49 Interrupt request I 4 53 Power fail I 1 54 Corrected read data I 1 55 Interval timer I 1 56 DMA request I 1 57 DMA grant O 1 58 Cache control I 1 59 FP Unit data I/O 6 65 FP Unit status I/O 2 67 Power I 6 73 Ground I 6 79 Clock in I 2 81 Test/Vss I 1 82 Clear write buffer O 1 83 Memory Error I 1 84 CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 62 INTERFACE 4.1.2 Data And Address Bus - 4.1.2.1 Data And Address Lines (DAL<31:00> H) - The Data and Address Bus (DAL<31:00>) is a bi-directional time-multiplexed bus. During the first part of a CPU read cycle, interrupt vector read, or CPU write cycle, DAL<31:30> indicate the length of the memory operand (00 = reserved for DMA hexword transfers, 01 = longword, 10 = quadword, 11 = reserved for DMA octaword transfers), and DAL<29:02> contain the LONGWORD address of the memory operand (DAL<29> distinguishes memory space from I/O space). DAL<01:00> are reserved (see the Memory Access Protocol) and may differ from the address implied by BM<3:0> L in the following circumstances: - During any cacheable read (always an aligned longword) - During a PTE read (always an aligned longword) - During the second cycle of an unaligned operation. During the first part of an interrupt acknowledge cycle, DAL<06:02> contain the IPL of the interrupt being acknowledged, DAL<31:30> and DAL<29:7,1:0> are 0. During the first part of an external processor register read or write cycle, DAL<7:2> contain the IPR number of the register that is being accessed, DAL<31:30> indicate the length of the memory operand, and DAL<29:8,1:0> are 0. During the second part of a CPU read, external processor register read, or interrupt acknowledge cycle, DAL<31:00> is used to receive incoming information. During the second part of a CPU write or external processor register write cycle, DAL<31:00> is used to transmit outgoing information. The DAL bus is also used to exchange information with an external floating point processor. Control of DAL<31:0> H is relinquished whenever DMG L is asserted. CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 63 INTERFACE 4.1.2.2 Cycle Status/Data Parity (CS/DP<3:0> L) - CS/DP<3:0> are time-multiplexed signals. During the first part of I/O cycles, CS/DP<3:0>, in conjunction with the WRITE signal (WR L), provide status about the current bus cycle. Specifically, WR L and CS/DP<2:0> mean the following when AS L is asserted: WR L CS/DP<2:0> Bus Cycle Type ---- ---------- -------------- H LLL request D-stream read H LLH reserved H LHL external IPR read H LHH interrupt acknowledge H HLL request I-stream read H HLH demand D-stream read (lock) H HHL demand D-stream read modify intent H HHH demand D-stream read (no lock or modify intent) L LLL reserved L LLH reserved L LHL external IPR write L LHH reserved for DMA device use L HLL reserved L HLH write unlock L HHL reserved L HHH write no unlock NOTE EXTERNAL IPRs ARE ACCESSED WITH THE SAME PROTOCOL AS MEMORY. THEREFORE, RDY L OR ERR L MUST BE ASSERTED TO TERMINATE THESE CYCLES; this is a change from the MicroVAX CPU chip. An external series terminating resistor (typical value 20 ohms to 50 ohms) is needed on these signals. Without these resistors, CSDP<3:0> may interfere with other CVAX signals. During the first part of a cacheable read cycle, CS/DP<3> provides status about which cache set is being allocated. CS/DP<3> is undefined during all other cycles. This signal allows a memory system to build a data coherent external cache. CS/DP<3> means the following when AS L is asserted: CS/DP<3> Cache set information -------- --------------------- L set 1 is being allocated H set 2 is being allocated During the second part of I/O cycles, CS/DP<3:0> L provide byte parity for the DAL bus data during a CPU read, CPU write, or external processor write cycle. No parity checking is done on a CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 64 INTERFACE CVAX/floating point unit data transfer, or external processor register read. Even parity is checked/generated on even bytes; odd parity on odd bytes. Even parity will drive a L when there are an even number of 1s in the byte's data; odd parity will drive a L for an odd number of 1s. CS/DP<3> L is the parity signal for DAL<31:24>, CS/DP<2> L for DAL<23:16>, CS/DP<1> L for DAL<15:8>, CS/DP<0> L for DAL<7:0>. On a CPU read, the CPU reads and checks data parity for the bytes specified by BM<3:0> L if Data Parity Enable (DPE L) is asserted. On a CPU write or external processor register write cycle, the CPU generates data parity for all bytes, irrespective of BM<3:0> L. NOTE DURING READ CYCLES, CS/DP<3:0> L MUST BE ASSERTED SYNCHRONOUSLY WITH RESPECT TO THE CHIP'S TIMING SAMPLING POINT AND THEREFORE MUST NOT CHANGE DURING THE SAMPLE WINDOW. Control of CS/DP<3:0> L is relinquished whenever DMG L is asserted. 4.1.2.3 Data Parity Enable (DPE L) - Data Parity Enable (DPE L) is a bi-directional signal. During a CPU read and interrupt acknowledge cycle, DPE L is asserted by external logic in conjunction with the DAL data in order to enable parity checking on the incoming DAL data. When negated, the DAL Parity lines are ignored. DPE L must be externally pulled up by an external resistor to the unasserted state, and therefore any interface which wants CVAX to check DAL H parity must actively assert DPE L. During a CPU write or external processor register write cycle, DPE L will be asserted by CVAX in conjunction with the DAL data in order to indicate that valid parity information is present. NOTE DURING A CPU READ CYCLE, DPE L MUST BE ASSERTED SYNCHRONOUSLY WITH RESPECT TO THE CHIP'S TIMING SAMPLING POINT AND THEREFORE MUST NOT CHANGE DURING THE SAMPLE WINDOW. An external series terminating resistor (typical value 20 ohms to 50 ohms) is needed on this signal. Without this resistor, the assertion of DPE L may interfere with other CVAX signals. Control of DPE L is relinquished whenever DMG L is asserted. CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 65 INTERFACE 4.1.3 Bus Control - 4.1.3.1 Address Strobe (AS L) - Address Strobe signal (AS L) is a bi-directional signal. CVAX drives AS L to provide timing and control information to external logic. During a CPU read, CPU write, external processor register read, external processor register write, or interrupt acknowledge cycle, the chip asserts AS L when the initial information on DAL<31:00> and CS/DP<3:0> L is valid. The chip negates AS L at the conclusion of the bus cycle. External logic drives AS L to provide an asynchronous address timing strobe. During a DMA cache invalidate cycle, AS L is asserted to latch the DMA address into the CPU. Control of AS L is relinquished whenever DMG L is asserted. 4.1.3.2 Data Strobe (DS L) - The Data Strobe signal (DS L) provides timing information for data transfers. During a CPU read (single or multiple transfers), external processor register read, or interrupt acknowledge cycle, the chip asserts DS L to indicate that DAL<31:00> and CS<3:0>/DP L are free to receive incoming data, and negates DS L to indicate that it has received and latched the incoming data. During a CPU write or external processor register write cycle, the chip asserts DS L to indicate that DAL<31:00> and CS/DP<3:0> L contain valid outgoing data, and negates DS L to indicate that the data is about to be removed. Control of DS L is relinquished whenever DMG L is asserted. NOTE An external series terminating resistor (typical value 20 ohms to 50 ohms) is needed on this signal. Without this resistor, the assertion of DS L may interfere with other CVAX signals. 4.1.3.3 Byte Mask (BM<3:0> L) - The byte mask signals (BM<3:0> L) specify which bytes of the DAL bus contain valid information during the second part of an I/O cycle. If BM<3> L is asserted, then DAL<31:24> contain valid data; if BM<2> L, then DAL<23:16>; if BM<1> L, then DAL<15:8>; if BM<0> L, then DAL<7:0>. During CPU read cycles, the byte CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 66 INTERFACE masks indicate which bytes of data, and which bits of parity, must be placed on the DAL and Data Parity lines; if this amounts to less than 32 bits, the other bytes of the DAL and bits of Data Parity are ignored. During a CPU write cycle, the byte masks specify which bytes of the DAL bus, and which Data Parity bits, contain valid data. Interrupt acknowledge cycles only read the two low order bytes. Therefore, BM<3:0> L will be asserted as 1100 (binary). External processor register cycles always read and write four bytes. Therefore, BM<3:0> L will be asserted during these cycles. BM<3:0> L must be latched by the assertion of AS L. Control of BM<3:0> L is relinquished whenever DMG L is asserted. NOTE These outputs are on the same VDD and VSS as the DALs, during a WRITE cycle VDD and VSS noise due to DALs switching from address to data may appear on these pins, causing them to be invalid at the time of the transition. 4.1.3.4 Write (WR L) - The Write signal (WR L) specifies the direction of data transfer on the DAL bus. If WR L is asserted, then the chip is driving data onto the DAL. If WR L is not asserted, the chip is not driving data onto the DAL. WR L can be used to control the direction input of the DAL transceivers. WR L must be latched by the assertion of AS L. Control of WR L is relinquished whenever DMG L is asserted. NOTE An external series terminating resistor (typical value 20 ohms to 50 ohms) is needed on this signal. Without this resistor, the assertion of WR L may interfere with other CVAX signals. 4.1.3.5 Data Buffer Enable (DBE L) - The Data Buffer Enable signal (DBE L) is used in conjunction with the WR L signal to control the external DAL transceivers. The chip asserts DBE L to enable the DAL transceivers, and negates it to disable them. Control of DBE L is relinquished whenever DMG L is asserted. CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 67 INTERFACE NOTE An external series terminating resistor (typical value 20 ohms to 50 ohms) is needed on this signal. Without this resistor, the assertion of DBE L may interfere with other CVAX signals. 4.1.3.6 Ready (RDY L) - External logic asserts the Ready signal (RDY L) to signal normal termination of the current CPU read, CPU write, external processor register read, external processor register write, or interrupt acknowledge cycle. During a CPU read, external processor read, or interrupt acknowledge cycle, this indicates that external logic has placed the required input data on the DAL bus in time for the next timing sampling point (see the timing diagrams). During a CPU write or external processor register write cycle, this indicates that the information on the DAL bus has been received and can be removed following the next timing sampling point. Upon assertion of RDY L, the chip terminates the current bus cycle and proceeds. External logic then negates RDY L. NOTE NOTE THAT READY L MUST BE ASSERTED SYNCHRONOUSLY WITH RESPECT TO THE CHIP'S TIMING SAMPLING POINT AND THEREFORE MUST NOT CHANGE DURING THE SAMPLE WINDOW; this is a change from the MicroVAX CPU chip. Only a high to low (assertion) transition is allowed on RDYL during a P4 that is part of a sample window. A low to high transition on RDYL during this time will cause unpredictable results! Therefore, RDYL must be negated (high) coming into a P4 that is part of a sample window if the intent is to have the CVAX CPU and CFPA see this signals negated. RDYL may be asserted coming into a P4 if it is to be asserted for the sample window. 4.1.3.7 Error (ERR L) - External logic asserts the Error signal (ERR L) to signal abnormal termination of the current CPU read, external processor read, external processor write, CPU write cycle, or interrupt acknowledge cycle. The interpretation of ERR L depends on whether RDY L is also asserted. CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 68 INTERFACE - ERR L asserted, RDY L asserted. This causes the chip to RETRY the current bus cycle. - ERR L asserted, RDY L not asserted. This causes the chip to ABORT the current bus cycle. During a CPU demand read or CPU write cycle, an abort causes a machine check. During a CPU request read, an abort causes the prefetch data to be discarded. During an external processor read cycle, an abort causes the read data to appear as 0. During an external processor write cycle, an abort is ignored. During an interrupt acknowledge cycle, an abort causes the interrupt request to be dismissed. The abort action will only be taken if RDY L is negated for two consecutive ERR L/RDY L sample points. In fact, if the abort response (ERR L asserted, RDY L negated) is detected at the first sample point, but RDY L is asserted at the second sample point, the cycle will be terminated and retried. This action eliminates a timing hazard that is possible when issuing a RETRY in systems that externally synchronize RDY L and ERR L. Whenever any cycle is retried, DMG L will be asserted in response to DMR L prior to retrying the cycle. When the CVAX CPU chip regains mastership of the DAL, the retried cycle is guaranteed to be immediately repeated unless it was the second longword read (non-preferred data in a quadword block) used to fill a cache entry. In this case, the cycle is never repeated and the partially allocated cache entry is invalidated. NOTE ERR L MUST BE ASSERTED SYNCHRONOUSLY WITH RESPECT TO THE CHIP'S TIMING SAMPLING POINT AND THEREFORE MUST NOT CHANGE DURING THE SAMPLE WINDOW; this is a change from the MicroVAX CPU chip. Only a high to low (assertion) transition is allowed on ERRL during a P4 that is part of a sample window. A low to high transition on ERRL during this time will cause unpredictable results! Therefore, ERRL must be negated (high) coming into a P4 that is part of a sample window if the intent is to have the CVAX CPU and CFPA see this signals negated. ERRL may be asserted coming into a P4 if it is to be asserted for the sample window. 4.1.4 System Control - CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 69 INTERFACE 4.1.4.1 Reset (RESET L) - External logic asynchronously asserts the Reset signal (RESET L) to force the chip to its initial power up state. NOTE THE NEGATION OF RESET L MUST BE EXTERNALLY SYNCHRONIZED SO THAT THE FIRST RISING EDGE OF CLKA FOLLOWING THE NEGATION OF RESET CORRESPONDS TO P1. When RESET L is asserted, DAL<31:0> H, DPE L, BM<3:0> L, WR L, and CS/DP<3:0> H lines are three-stated; AS L, DS L, DBE L, DMG L, CWB L are driven to the negated state. When RESET L is negated, the chip enters the restart process with the restart code = 3 (RESET L asserted). 4.1.4.2 Halt (HALT L) - External logic asserts the Halt signal (HALT L) to transfer control to console macrocode. At the conclusion of the current macroinstruction, the chip enters the restart process with the restart code = 2 (HALT L asserted). HALT L is edge- rather than level-sensitive, is sampled during P2 of every microcycle, and is used internally during P1 (internal synchronizer settling time is two internal clock phases). 4.1.5 Interrupt Control - 4.1.5.1 Interrupt Request (IRQ<3:0> L) - The Interrupt Request signals (IRQ<3:0> L) allow external logic to input interrupt requests to the chip. IRQ<3> L corresponds to BR7 and interrupts at IPL17; IRQ<2> L to BR6, IPL16; IRQ<1> L to BR5, IPL15; IRQ<0> L to BR4, IPL14. When taken, interrupt requests are acknowledged by an interrupt acknowledge cycle. IRQ<3:0> L are level-sensitive, are sampled during P2 of every microcycle, and are used internally during P1 (synchronizer settling time is two internal clock phases). 4.1.5.2 Power Fail (PWRFL L) - The Power Fail signal (PWRFL L) allows external logic to signal a power fail condition to the chip. PWRFL L interrupts at IPL1E (SCB vector 0C hex). A power fail interrupt is NOT acknowledged CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 70 INTERFACE by the chip. PWRFL L is edge- rather than level-sensitive, is sampled during P2 of every microcycle, and is used internally during P1 (synchronizer settling time is two internal clock phases). 4.1.5.3 Corrected Read Data (CRD L) - The Corrected Read Data signal (CRD L) allows external logic to signal an ECC error to the chip. CRD L interrupts at IPL1A (SCB vector 54 hex). A corrected read data interrupt is NOT acknowledged by the chip. CRD L is edge- rather than level-sensitive, is sampled during P2 of every microcycle, and is used internally during P1 (synchronizer settling time is two internal clock phases). 4.1.5.4 Interval Timer (INTTIM L) - The Interval Timer signal (INTTIM L) allows external logic to signal an interval timer roll over to the chip. INTTIM L interrupts at IPL16 (SCB vector C0 hex). An interval timer interrupt is NOT acknowledged by the chip. INTTIM L is edge- rather than level-sensitive, is sampled during P2 of every microcycle, and is used internally during P1 (synchronizer settling time is two internal clock phases). INTTIM L is only recognized when the interrupt enable bit in the ICCS register (ICCS<6>) is set. 4.1.5.5 Memory Error (MEMERR L) - The Memory Error signal (MEMERR L) allows external logic to signal an memory error to the chip. MEMERR L permits the implementation of a memory subsystem with multiple write buffers or delayed writes. When the CPU writes, this type of memory subsystem latches the data and address and asserts RDY L immediately. Then, if an error occurs, it is reported via the MEMERR interrupt. MEMERR L interrupts at IPL1D (SCB vector 60 hex). A Memory Error interrupt is NOT acknowledged by the chip. MEMERR L is edge- rather than level-sensitive, is sampled during P2 of every microcycle, and is used internally during P1 (synchronizer settling time is two internal clock phases). 4.1.6 DMA Control - CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 71 INTERFACE 4.1.6.1 DMA Request (DMR L) - The DMA Request signal (DMR L) is asserted by external logic which wishes to take control of the DAL bus and related control signals for DMA or other purposes. DMR L is level-sensitive, is sampled during P4 of every microcycle, and is used internally during P3 (synchronizer settling time is two internal clock phases). 4.1.6.2 DMA Grant (DMG L) - The DMA Grant signal (DMG L) is asserted by the chip to grant control of the DAL bus and related control signals to external logic. The chip 3-states the DAL bus and the following strobe signals: AS L, DS L, BM<3:0> L, DBE L, DPE L, CS/DP<3:0> L, and WR L. When external logic negates DMR L, the chip responds by negating DMG L and then starts the next bus cycle. The CVAX CPU chip guarantees that back-to-back DMA cycles will not starve the CPU from the bus. One CVAX CPU cycle will always execute between the DMA cycles. NOTE An external series terminating resistor (typical value 20 ohms to 50 ohms) is needed on this signal. Without this resistor, the assertion of DMG L may interfere with other CVAX signals. 4.1.7 Cache Control (CCTL L) - CCTL L has two functions: during DMA write operation, it is used to start a conditional cache invalidate operation; during CPU read cycles, it is used to prevent data caching. 4.1.7.1 Conditional Cache Invalidate - Since the CVAX CPU chip has an internal cache, it must be able to monitor external (DMA) write traffic in order to prevent cache data from becoming stale. In such a situation, a DMA device writes a memory location which is also stored in the on chip cache. Only memory is updated. Therefore, in order to guarantee that the cache is free of stale data, this address "collision" must be detected, and the corresponding cache entry must be invalidated. Each conditional invalidate operation detects a collision on a quadword cache entry. Two consecutive conditional invalidate cycles can be used to detect a collision on a naturally aligned CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 72 INTERFACE octaword. A DMA device asynchronously drives an address on the DAL and then asserts AS L in order to provide an asynchronous address latch control for the chip. The DMA device initiates a conditional invalidate operation by asserting CCTL L. The alternate quadword defined by inverting address bit <3> can also be conditionally invalidated if CCTL L is asserted twice during the DMA operation. A DMA device keeps AS L asserted throughout the conditional invalidate operation and negates it to end the quadword or octaword DAL transfer. When used to initiate conditional invalidate cycles, CCTL L is edge-sensitive, is sampled during P4 of every microcycle, and is used internally during P3 (synchronizer settling time is two internal clock phases). 4.1.7.2 Prevent Data Caching - External logic asserts CCTL L to prevent storing the result of the current CPU read cycle in the internal cache. CCTL L must be asserted coincident with the first transfer of data during a multiple transfer read operation if either transfer is to be prevented for storing a result in the cache. Therefore, the smallest piece of data that can be prevented from being stored in the cache is a quadword. I/O space and read lock references are never cached, irrespective of state of CCTL L. NOTE WHEN USED TO PREVENT DATA CACHING, CCTL L IS LEVEL-SENSITIVE AND MUST BE ASSERTED SYNCHRONOUSLY WITH RESPECT TO THE CHIP'S TIMING SAMPLING POINT. 4.1.8 Floating Point Unit Control - An optional Floating Point Unit (CFPA) can be attached to the CVAX CPU chip in order to accelerate certain integer and floating point instructions. 4.1.8.1 CFPA Data Lines (CPDAT<5:0> H) - The CFPA Data Lines carry opcode and control information to the floating point unit and return condition code and exception status to the CVAX CPU chip. The CPU chip drives these lines until it is waiting for return data. The CFPA drives these lines when it is returning status. In both cases, CPDAT<5:0> H is sampled synchronously by the destination at the beginning of P1. CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 73 INTERFACE 4.1.8.2 CFPA Status Lines (CPSTA<1:0> H) - The CFPA Status Lines are sampled synchronously at the beginning of P1 and inform the destination how to interpret CPDAT<5:0> H as is indicated below: CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 74 INTERFACE CVAX CPU drives lines --------------------- CPSTA<1:0> H Function CPDAT<5:0> H ------------ -------- ------------- 00 Operation <5:4> Address alignment code encoded on CPDAT<5:0> H <3> = 0 no action <3> = 1 CPU ready for result <2> = 0 PSL<6> is cleared (valid only when CPDAT<0>=1 or CPDAT<1>=1) <2> = 1 PSL<6> is set (valid only when CPDAT<0>=1 or CPDAT<1>=1) <1> = 0 no action <1> = 1 DAL<31:0> contains CFPA operand <0> = 0 no action <0> = 1 DAL<5:0> contains CFPA short literal; DAL<31:6> are 0's 01 Integer <5:0> Integer opcode opcode on CPDAT<5:0> 10 F/D floating <5:0> Floating point opcode point opcode on CPDAT<5:0> 11 G floating <5:0> Floating point opcode point opcode on CPDAT<5:0> CFPA drives lines ----------------- CPSTA<1:0> H Function CPDAT<5:0> H Comment ------------ -------- ------------- ------- 00 Result not reserved CFPA keeps driving lines ready 10 illegal protocol error generated 01 illegal protocol error generated 11 Condition <5> = 0 the result clears the PSL N bit codes <5> = 1 the result sets the PSL N bit ready <4> = 0 the result clears the PSL Z bit <4> = 1 the result sets the PSL Z bit <3> = 0 the result clears the PSL V bit <3> = 1 the result sets the PSL V bit (integer overflow/ACB condition met) CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 75 INTERFACE <2:0> Status ----- ------ 000 protocol error 001 reserved opcode 010 reserved operand trap 011 divide by zero 100 floating point overflow 101 floating point underflow 110 protocol error 111 no error CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 76 INTERFACE 4.1.9 Miscellaneous - 4.1.9.1 Power - These inputs supply +5V to the chip. Extreme care must be taken to connect the power pins together, i.e., use very short wires or a power plane. 4.1.9.2 Ground - These inputs supply ground to the chip. Extreme care must be taken to connect the ground pins together, i.e., use very short wires or a power plane. 4.1.9.3 Clock In (CLKA,CLKB) - This input supplies basic clock timing to the chip. CLKA and CLKB are MOS level square wave signals that are 180 degrees phase shifted. 4.1.9.4 Clear Write Buffer (CWB L) - CWB L has multiple uses. When TEST H is negated, CWB L asserts when the chip detects a condition which requires an external write buffer to flush; when TEST H is asserted (test mode), CWB L is driven with test state. 4.1.9.4.1 Write Buffer Support - A Write buffer (external to the chip) accepts memory writes from the processor, buffer them for some period of time, and finally send the buffered write data to memory. Write buffers act as a small cache of the data most recently written by a processor. As such, they introduce a temporary inconsistency between the stale data in memory and the data in the write buffers. There are two general reasons why a write buffers must be flushed: 1. To make changes to shared memory data visible to other processors and/or devices. 2. To report errors detected during writes of the buffered data in the same processor mode and/or process context that existed when the write was originally issued by the processor. CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 77 INTERFACE Some of the conditions in which a write buffer must be flushed can only be detected by the CVAX CPU. CWB L asserts for these conditions (assuming TEST H is negated). 1. Execution of a CHMx, REI, LDPCTX, or SVPCTX macroinstruction 2. Start of an interrupt, exception, or abort 3. Write to the MAPEN internal processor register 4. Entry to console, including kernel HALT In each of the above situations, the assertion of CWB L will always occur after the completion all memory writes that must be guaranteed to clear out of an external write buffer. A system interface that implements an external write buffer cannot rely solely on CWB L to signal all of the conditions which require the write buffer to be written to memory. The cycle status and address information must also be examined in order to detect inter-processor interrupts, interlocked read or write cycles, and I/O space read or write cycles. 4.1.9.4.2 Test Output - When TEST H is asserted, CWB L is driven with internal state information. Refer to section 4.5 for additional test logic information. 4.1.9.5 Test (TEST H) - TEST H is used to control the internal CVAX CPU chip test logic. The test logic enables test hardware to read internal chip state that is not normally observable on the external pins. The operation of the test pin is documented in section 4.5. This pin also serves as the VSS supply for AS L and should be treated as a VSS pin in normal operation. 4.2 Bus Cycle Descriptions The CVAX CPU chip supports the following types of bus cycles: idle; single transfer CPU read; multiple transfer CPU read; single transfer CPU write; external processor register read; external processor register write; interrupt acknowledge; DMA grant; and cache invalidate. CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 78 INTERFACE 4.2.1 Idle Cycle - An idle cycle requires two CLKA cycles. The DAL bus is undefined. The bus control signals are unasserted. 4.2.2 Single Transfer CPU Read Cycle - In a single transfer CPU read cycle, the chip reads at most one longword from main memory or an I/O device. A single transfer CPU read cycle requires a minimum of four CLKA cycles and may last longer, in increments of two CLKA cycles. The chip drives the physical LONGWORD address onto DAL<29:02>. DAL<31:30> are asserted to 01 to indicate single longword transfer, BM<3:0> L are asserted as required, and WR L is unasserted. The chip asserts AS L, indicating that the physical address is valid. The chip then asserts DBE L, enabling the external interface to drive the DAL lines and then DS L, indicating that the DAL bus is free to receive incoming data. The chip then samples for cycle complete once every two clock phases, starting at the next possible P1 edge. If no error occurs, external logic responds by placing the required data on DAL<31:00> and CS/DP<3:0> L, asserting DPE L if DAL parity is to be checked, asserting RDY L, and negating ERR L. The chip reads the data from the DAL bus and corresponding byte parity information from CS/DPE<3:0> L. Parity is checked if DPE L is asserted. If a parity error occurs, the appropriate error information is logged in MSER, the chip ignores the data on DAL<31:00>, and generates a machine check if the cycle was a demand read cycle. If an error occurs, external logic responds by asserting ERR L with RDY L negated. The chip ignores the data on DAL<31:00> and generates a machine check if the cycle was a demand read cycle. NOTE An error will only be recognized if RDY L is negated for two consecutive P1 sample points. If the error response (ERR L asserted, RDY L negated) is detected at the first P1 sample point, but RDY L is asserted at the second P1 sample point, the cycle will terminate according to the retry protocol detailed below. To request a retry, external logic must assert both RDY L and ERR L. Retrying a read cycle can eliminate DAL deadlocks because the chip guarantees that DAL arbitration occurs before the cycle is restarted (DMG L will be granted if DMR L is asserted). Note that certain request read cycles will not reissue a bus cycle if they are retried. Specifically, if the retry occurs during an I-stream request cycle, the bus cycle may CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 79 INTERFACE not reissue the cycle since the CPU may have executed a branch instruction. All retries that occur on demand cycles will reissue the cycle. In all read cycles, DAL arbitration occurs after the read cycle is terminated. Irrespective of how a single transfer CPU read cycle is terminated, the chip finishes the cycle by negating AS L, DBE L and DS L. 4.2.3 Multiple Transfer CPU Read Cycle - In a multiple transfer CPU read cycle, the chip reads two longwords (one quadword) from main memory. A multiple transfer CPU read cycle requires a minimum of six CLKA cycles and may last longer. Each longword transfer may be independently stretched in increments of two CLKA cycles. Note that I/O space read references always occur as single transfer read cycles. The chip drives the physical address of the preferred LONGWORD that is to be accessed onto DAL<29:02>. Note this address can be aligned to either longword address within the quadword block. DAL<31:30> are asserted to 10 to indicate a quadword transfer. BM<3:0> L are asserted, and WR L is unasserted. The chip asserts AS L, indicating that the physical address is valid, and then DBE L, indicating that the external interface can drive information on the DAL. For each of the multiple transfers, the chip asserts DS L to indicate that the DAL bus is free to receive incoming data, and then samples for individual transfer complete once every two clock phases, starting at the next possible P1 edge. If no error occurs, external logic responds on each transfer by placing the required data on DAL<31:00> and CS/DP<3:0> L, asserting DPE L if DAL parity is to be checked, asserting CCTL L if data caching is to be prevented, asserting RDY L, and negating ERR L. The chip reads the data from the DAL bus and corresponding byte parity information from CS/DPE<3:0> L, and negates DS L. Parity is checked if DPE L is asserted. If a parity error occurs, the appropriate error information is logged in MSER, the chip ignores the data on DAL<31:00>, and generates a machine check if the cycle was a demand read cycle. If data caching was not prevented, the CPU then continues on to read the additional data by asserting DS L again irrespective of a DAL parity error. The second data is ignored if a DAL parity error was detected on the first transfer. If data caching was prevented, the cycle immediately terminates without reading the second longword of data. If an error occurs during either transfer, external logic responds by asserting ERR L with RDY L negated. The CPU ignores the data on DAL<31:00>, terminates the cycle without reading any additional data, and generates a machine check if the cycle was a demand read cycle. Note that only the first transfer can be a demand cycle. CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 80 INTERFACE NOTE An error will only be recognized if RDY L is negated for two consecutive P1 sample points. If the error response (ERR L asserted, RDY L negated) is detected at the first P1 sample point, but RDY L is asserted at the second P1 sample point, the cycle will terminate according to the retry protocol detailed below. To request a retry, external logic must assert both RDY L and ERR L. Retrying a read cycle can eliminate DAL deadlocks because the chip guarantees that DAL arbitration occurs before the cycle is restarted (DMG L will be granted if DMR L is asserted). Note that if the retry occurs during the second longword transfer, the read will not be reissued. The chip sends out an address only on the initial longword (preferred) transfer of a multiple transfer read cycle. The address associated with the second (cache fill) transfer is implied and therefore is not driven out of the chip. The implied address is generated by inverting address bit<2> of the preferred address. All references therefore stay within a quadword block. For example, if the initial longword address in a quadword transfer is 0007FB36, the subsequent implied addresses is 0007FB32. Normally, a multiple transfer cycle reads two longwords of data. However, the cycle terminates after the first data transfer if ERR L is asserted and RDY L is negated (memory error), or if CCTL L is asserted (prevent data caching). The cycle does not terminate early if a DAL parity error is detected on the first transfer. CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 81 INTERFACE A summary of all possible multiple transfer cycle responses follows: Condition | Action --------- | ------ | 1=asserted | 0=negated | X=don't care | DAL | On On Parity | First Second CCTL RDY ERR ERROR | Reference Reference ---- --- --- ----- | --------- --------- X 0 0 X | wait for data wait for data | X 0 1 X | machine check if demand no machine check | invalidate cache entry invalidate cache entry | no second reference | 0 1 0 0 | no machine check no machine check | update cache update cache | proceed to second reference | 1 1 0 0 | no machine check no machine check | invalidate cache entry update cache | no second reference | 0 1 0 1 | machine check if demand no machine check | invalidate cache entry invalidate cache entry | log error in MSER log error in MSER | proceed to second reference | 1 1 0 1 | machine check if demand no machine check | invalidate cache entry invalidate cache entry | log error in MSER log error in MSER | no second reference | X 1 1 X | no machine check no machine check | no cache change invalidate cache entry | no second reference - retry no retry Irrespective of how a multiple transfer CPU read cycle is terminated, the chip finishes the cycle by negating AS L, DBE L and DS L. Note that DBE L is not negated in between each transfer. 4.2.4 CPU Write Cycle - In a CPU write cycle, the chip writes information to main memory or an I/O device. A CPU write cycle requires a minimum of four CLKA cycles and may last longer, in increments of two CLKA cycles. The chip drives the physical LONGWORD address onto DAL<29:02>. BM<3:0> L are asserted as required, DAL<31:30> are CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 82 INTERFACE driven as 01 to indicate longword transfer, and WR L is asserted. The chip asserts AS L, indicating that the physical address is valid, and then DBE L, indicating that the write data can be driven on an external bus. The chip then drives the output data onto DAL<31:00>, drives the byte parity information on CS/DP<3:0> L, asserts DPE L indicating that valid parity information is available, and asserts DS L, indicating the Data bus contains valid data. The chip then samples for cycle complete once every two clock phases, starting at the next possible P1. If no error occurs, external logic responds by reading the data from the DAL bus, asserting RDY L and negating ERR L. If an error occurs, external logic responds by asserting ERR L with RDY L negated. Aborting a write cycle will generate a machine check. Note that a DAL parity error can be reported back to the CPU by asserting ERR L and negating RDY L. NOTE An error will only be recognized if RDY L is negated for two consecutive P1 sample points. If the error response (ERR L asserted, RDY L negated) is detected at the first P1 sample point, but RDY L is asserted at the second P1 sample point, the cycle will terminate according to the retry protocol detailed below. To request a retry, external logic must assert both RDY L and ERR L. DAL arbitration occurs after the write operation is terminated. Irrespective of how a CPU write cycle is terminated, the chip finishes the cycle by negating AS L, DBE L, and DS L. 4.2.5 External Processor Register Read Cycle - An external processor register read cycle is initiated whenever a category 3 processor register (see section 2.8) is read using a MFPR instruction. This cycle requires a minimum of four CLKA cycles and may last longer, in increments of two CLKA cycles. The chip drives the processor register number onto DAL<7:2>. DAL<31:30> are asserted to 01 to indicate longword transfer, DAL<29:8,1:0> are 0, BM<3:0> L are all asserted, and WR L is unasserted. The chip asserts AS L, indicating that the register number is valid, and then DBE L, indicating that read data can be driven on the DAL. The chip then asserts DS L, indicating that the DAL bus is free to receive incoming data. The chip then samples for cycle complete once every two clock phases, at the next possible P1. If the processor register is implemented, external logic CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 83 INTERFACE responds by placing the required data on DAL<31:00>, asserting RDY L, and negating ERR L. The chip reads the data from the DAL bus. If the processor register is not implemented, external logic responds by asserting ERR L with RDY L negated. The chip ignores the data on DAL<31:00> and internally forces the result to zero. A detected parity error will force the result to zero and will not get reported. Therefore, it is recommended that DPE L remain negated during a processor register read. NOTE The not implemented response will only be recognized if RDY L is negated for two consecutive P1 sample points. If this response (ERR L asserted, RDY L negated) is detected at the first P1 sample point, but RDY L is asserted at the second P1 sample point, the cycle will terminate according to the retry protocol detailed below. To request a retry, external logic must assert both RDY L and ERR L. DAL arbitration occurs after the initial read cycle is terminated. Irrespective of how an external processor read cycle is terminated, the chip finishes the cycle by negating AS L, DBE L and DS L. 4.2.6 External Processor Register Write Cycle - An external processor register write cycle is initiated whenever a category 3 processor register (see section 2.8) is written using a MTPR instruction. This cycle requires a minimum of four CLKA cycles and may last longer, in increments of two CLKA cycles. The chip drives the processor register number onto DAL<7:2>. BM<3:0> L are all asserted, DAL<31:30> are driven as 01 to indicate longword transfer, DAL<29:8,1:0> are 0, and WR L is asserted. The chip asserts AS L, indicating that the register number is valid, and then asserts DBE L, indicating that the write data can be driven on an external bus. The chip then drives the write data onto DAL<31:00> and asserts DS L, indicating the DAL contains valid data. The chip then samples for cycle complete once every two clock phases, starting at the next possible P1. If the processor register is implemented, external logic responds by reading the data from the DAL bus, asserting RDY L, and negating ERR L. If the processor register is not implemented, external logic either responds as is indicated above or asserts ERR L and negates RDY L. Both responses have the same effect; no special action is taken. CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 84 INTERFACE NOTE The not implemented response (ERR L asserted, RDY L negated) will take no special action only if RDY L is negated for two consecutive P1 sample points. If this response is detected at the first P1 sample point, but RDY L is asserted at the second P1 sample point, the cycle will terminate according to the retry protocol detailed below. To request a retry, external logic must assert both RDY L and ERR L. DAL arbitration occurs after the initial write cycle is terminated. Irrespective of how an external processor write cycle is terminated, the chip finishes the cycle by negating AS L, DBE L and DS L. 4.2.7 Interrupt Acknowledge Cycle - An interrupt acknowledge cycle has the same structure as a single transfer CPU read cycle. DAL<6:2> is driven out with the IPL level of the interrupt being acknowledged (IRQ<3> L is IPL 17, IRQ<2> L is IPL 16, IRQ<1> L is IPL 15, IRQ<0> L is IPL 14), and DAL<31:30> are driven with 01 and DAL<29:7,1:0> are driven with zeros. The data read in is used to generate the vector and new IPL for the interrupt sequence. Bits <15:02> of the incoming data are used to create the vector offset within the System Control Block. The new PSL priority level is determined by either the external interrupt request level that caused the interrupt or by bit <0> of the value supplied by external hardware. If bit<0> is 0, the new IPL level is determined by the interrupt request level being serviced. IRQ<3> sets the IPL to 17 (hex); IRQ<2>, 16 (hex); IRQ<1>, 15 (hex); and IRQ<0>, 14 (hex). If bit<0> of the value supplied by external hardware is 1, then the new IPL is forced to 17 (hex). Bits <31:16,01> of the incoming data are ignored. Assertion of ERR L in proper combination with RDY L causes the bus cycle to be retried or aborted. An abort causes the DAL data to be ignored, and the chip to continue as if the interrupt request never occurred (passive release of the interrupt request). A detected DAL parity error will also cause a passive release and will not be reported. Therefore, it is recommended that DPE L remain negated during a processor register read. 4.2.8 DMA Grant Cycle - The chip can relinquish its control of the DAL bus and related control signals upon request from a DMA device or another CPU. The external device requests control of the bus by asserting DMR CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 85 INTERFACE L. At the conclusion of the current bus cycle, the chip responds by three-stating DAL<31:00>, AS L, DS L, WR L, and DBE L, BM<3:0> L and DP/CS<3:0> L, and asserts DMG L. The external device may now use the DAL bus to transfer data. To return control of the DAL bus to the chip, the external device and negates DMR L. The chip responds by negating DMG L and starting the next bus cycle. 4.2.9 Cache Invalidate Cycles - External logic initiates a conditional invalidate operation to detect and invalidate stale data that is stored in the cache. A conditional invalidate cycle uses a minimum of six CLKA cycles. Once DMG L is asserted by the chip, external logic asynchronously drives the physical address onto DAL<31:0>, asynchronously asserts AS L to latch the address into the chip, and then asynchronously asserts CCTL L to start a conditional invalidate cycle. The chip then invalidates the quadword cache entry selected by the DMA address if the location is stored in the cache. External logic negates CCTL L and then optionally asserts CCTL L again to conditionally invalidate the alternate quadword formed by inverting address bit <3>. This allows external logic to detect and invalidate stale data stored in any naturally aligned octaword. The cycle ends when external logic negates both AS L and CCTL L. NOTE If a cache parity error (only tag parity is checked) is detected during the conditional invalidate operation, no machine check is generated, no invalidate occurs, and the error is logged in MSER. The chip detects and invalidates quadword stale data in six clock phases. Therefore, the maximum cache invalidate rate can not exceed 8 byte/six CLKA cycles. 4.3 Memory Access Protocol The 28-bit address provided by the CVAX CPU chip on DAL<29:02> is a LONGWORD address which uniquely identifies one of up to 268,435,456 32-bit memory locations. The chip provides four byte masks, BM<3:0> L, to facilitate byte accesses within 32-bit memory locations. The chip imposes no restrictions on data alignment. Any data item, regardless of size, may be placed starting at any memory address (except for the aligned operands of ADAWI and the interlocked queue instructions). CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 86 INTERFACE Memory is viewed as four parallel eight-bit banks, each of which receives the longword address DAL<29:02> in parallel. Each bank reads or writes one byte of the data bus (DAL<31:00>), provided that its byte mask signal is asserted. This is illustrated in the following diagram: BM<3> L BM<2> L BM<1> L BM<0> L | | | | | | | | o o o o +-------+-----------+-----------+-----------+-----------+ | | 8 bits | 8 bits | 8 bits | 8 bits | | +-----------+-----------+-----------+-----------+ | | | | | | | +-----------+-----------+-----------+-----------+ DAL<29:02> ---> | | | | | | | +-----------+-----------+-----------+-----------+ : : : : : : : : : : | +-----------+-----------+-----------+-----------+ | | | | | | | +-----------+-----------+-----------+-----------+ | | | | | | | +-----------+-----------+-----------+-----------+ | | | | | | +-------+-----------+-----------+-----------+-----------+ ^ ^ ^ ^ | | | | V V V V DAL<31:24> DAL<23:16> DAL<15:08> DAL<07:00> Any single transfer CPU read or CPU write falls into one of the following categories: byte access, word access within a longword, word access across longwords, aligned longword access, unaligned longword access. (Quadword data is accessed with two successive longword accesses, with no optimization.) Byte accesses, word accesses within a longword, and aligned longword accesses require one bus cycle. Word accesses which cross a longword boundary, and unaligned longword accesses, require two bus cycles. The exact signal usage is shown in the following chart: CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 87 INTERFACE Single Transfer Access Type Cycle DAL<31:30> DAL<29:02> BM<3> L BM<2> L BM<1> L BM<0> L ----------- ----- ---------- ---------- ------- ------- ------- ------- byte 1 01 A<29:02> if A<1:0>=11 if A<1:0>=10 if A<1:0>=01 if A<1:0>=00 word within 1 01 A<29:02> if A<1:0>=10 if A<1:0>=10 if A<1:0>=0X if A<1:0>=00 longword [A<1:0> ne 11] or A<1:0>=01 aligned longword 1 01 A<29:02> L L L L [A<1:0> = 00] word across 1 01 A<29:02> L H H H longwords 2 A+4<29:02> H H H L [A<1:0> = 11] unaligned 1 01 A<29:02> L if A<1:0>=01 if A<1:0>=01 H longword or A<1:0>=10 2 01 A+4<29:02> H if A<1:0>=11 if A<1:0>=10 L [A<1:0> ne 00] or A<1:0>=11 Accesses requiring more than one bus cycle are performed sequentially, with no computation in between. However, DMA grants may occur between the bus cycles of an unaligned reference. All multiple transfer CPU read cycles read exactly two aligned longwords. Therefore, BM<3:0> L are asserted for each data transfer, DAL<31:30> H are driven as 10 and DAL<1:0> are not specified. DMA grants can not occur between the individual transfers. 4.3.1 I-stream Prefetching - The CVAX CPU chip contains a twelve byte I-stream prefetch buffer organized as three aligned longwords. A request I-stream prefetch cycle will be generated only when an aligned longword is empty. Up to six bytes at a time can be retired from the prefetch buffer. 4.4 CFPA Protocols 4.4.1 Passing Opcode Information To The CFPA - Opcode information must be passed to the CFPA whenever it is going to execute or accelerate any instruction. All floating point and some integer instructions pass opcode information when CFPA activity is desired (assuming the CFPA is present). In either case, only the six lower order opcode bits are passed to the CFPA. the CPU chip drives an f/d_floating point opcode on CPDAT when CPSTA<1:0> H=10; a g_floating point opcode when CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 88 INTERFACE CPSTA<1:0>=11; and an integer opcode when CPSTA<1:0> H=01. Note that the integer instructions that are accelerated by the CFPA are DIVL2, DIVL3, MULL2, MULL3, and EMUL. 4.4.2 Passing Operands To The CFPA - Operands that are to be passed to the CFPA can come from three sources: memory, the internal cache, or the general purpose registers. The CPU chip drives CPSTA<1:0> H=00, PSL<6> on CPDAT<2> H, and either CPDAT<1> H=1 when the next CFPA operand data is on DAL<31:0> or CPDAT<0> when the next CFPA operand data is a short literal on DAL<5:0> H (DAL<31:6> will be zero). If the source of the operand is either memory or the internal cache, CPDAT<5:4> are driven with the two low order address bits of the reference; otherwise the source is the general purpose registers and CPDAT<5:4> are driven as 00. The CFPA must align all unaligned data. If the data is coming from memory (AS L is asserted), the CFPA reads the DALs according to the full memory read protocol (RDY L and/or ERR L asserted); otherwise, the data is coming from the CPU chip (internal cache or the general purpose registers), is driven on the DALs at P3 and is sampled by the CFPA at the next P1. If the source of the operand is either memory or the internal cache and a parity error is detected by the CPU chip, the chip aborts the CFPA operation, and never signals the CFPA for the current result. The CFPA is reset when the CPU chip sends a new CFPA opcode. In summary, CPDAT<5:0> H are encoded as follows while operands are being passed to the CFPA: CPDAT<5:0> ---------- <5:4> Address alignment code <3> = 0 will always be negated <2> = 0 PSL<6> is cleared = 1 PSL<6> is set <1> = 0 no action = 1 DAL<31:0> is CFPA operand <0> = 0 no action = 1 DAL<5:0> is short literal; DAL<31:6> are 0's. 4.4.3 Passing Results Back From The CFPA - The CPU chip informs the CFPA when it is ready for a result by asserting CPSTA<1:0> H=00 and CPDAT<3>=1. The CPU chip then gives up ownership of CPDAT<5:0> H, CPSTA<1:0> H, and DAL<31:0> H by three-stating these lines at the next P2 edge; the CFPA CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 89 INTERFACE gains ownership of CPDAT<5:0> H and CPSTA <1:0> H by driving them at the next P3 edge. DAL<31:0> H remains three-stated while the CPU chip waits for the CFPA result. While waiting, the CPU chip can grant DMG L on a P4 edge. If no DMG L is granted, the CPU chip continuously samples the CFPA CPSTA and CPDAT lines on each P1 edge; if granted, the CPSTA and CPDAT lines are ignored. The CFPA asserts CPSTA<1:0> H=00 at a P3 edge to indicate that the result is not ready; and CPSTA<1:0> H=11, to indicate that they are ready. Any other encoding will generate a protocol error. If the CFPA indicates that the condition codes are ready (P3) at the same time that the CPU chip grants DMG L (P4), the CFPA repeats the response until DMG L is negated; otherwise, the CFPA three-states CPDAT<5:0> H and CPSTA<1:0> H on the next P2 edge. The CPU then gains control of CPDAT<5:0> H and CPSTA<1:0> H on the next P3 edge. Once the CPU chip detects that the condition code results are ready, the CPDAT lines are used to determine the response, and DMG L will not be granted until the end of the operation. CPDAT<5:0> H are encoded as follow: CPDAT<5> = 0 the result clears the PSL N bit. = 1 the result sets the PSL N bit. CPDAT<4> = 0 the result clears the PSL Z bit. = 1 the result sets the PSL Z bit. CPDAT<3> = 0 the result clears the PSL V bit = 1 the result sets the PSL V bit (integer overflow/ACB condition met) CPDAT<2:0> Status Data Transfer ---------- ------ ------------- 000 protocol error aborted 001 reserved opcode aborted 010 reserved operand trap aborted 011 divide by zero aborted 100 floating point overflow aborted 101 floating point underflow aborted 110 reserved - protocol error aborted 111 no error continue If CPDAT<2:0> H indicates protocol error, reserve opcode, reserved operand trap, divide by zero, floating point overflow, or floating point underflow, no data is transferred; otherwise, all result data is return over the DAL on consecutive cycle immediately following the condition code result. In any case, the CFPA gives up CPDAT and CPSTA ownership by three-stating these lines at the next P2 edge; the CPU chip gains ownership on the next P3 edge. Note that the CFPA will never report a floating point underflow error if PSL<6> is cleared. A single unaligned longword is transferred for a single precision result (F), and two unaligned longwords are CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 90 INTERFACE transferred for a double precision result (D or G). The CPU chip aligns the data and performs the final transfer if the ultimate destination of the CFPA data is memory. 4.4.4 CFPA Present Indication - The CFPA is an optional coprocessor. The CFPA informs the CPU chip that it is present when RESET L is asserted. Specifically, the CFPA actively drives CPDAT<5:0> H and CPSTA<1:0> H to L when RESET L is asserted. In parallel, the CPU chip also actively drives CPDAT<5:0> H and CPSTA<1> H to L while providing a weak pull up (H) on CPSTA<0> H. Therefore, if no coprocessor is present, CPSTA<0> H is read as H; otherwise, the CFPA overdrives CPSTA<0> H so that it reads as L. 4.4.5 CFPA Forced Termination - There are several error conditions that are detected in the CPU chip which cause the CFPA to terminate the execution of a floating point or accelerated integer instruction. - RESET L is asserted - CFPA operand generates a reserved addressing mode fault - CFPA operand generates an address translation fault - CFPA operand access causes a machine check abort - CFPA operand access causes a cache or DAL parity error The CFPA terminates all execution and resets whenever the CPU chip sends an opcode on CPDAT<5:0> irrespective of the CFPA state, and whenever RESET L is asserted. CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 91 INTERFACE 4.4.6 CFPA Interface Overhead - Symbol Meaning ------ ------- DOB data on DAL bus opcode opcode on CPDAT bus nop null cycle rr ready for result cc condition codes ready cpr CFPA result lcpr last CFPA result adr DAL address cdata cache or register data data demand D-stream data from memory fill request D-stream data from memory cpd CFPA data hiz DALs three-state -- DAL not specified 4.4.6.1 Opcode Transfer - Opcode Transfer cycle | 1 | CP lines opcode DAL -- CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 92 INTERFACE 4.4.6.2 Passing Operands To CFPA - Single Precision Register Transfer - 1st operand or 2nd & 3rd operand if not preceded by memory transfer (cache miss) cycle | 1 | CP lines DOB DAL cdata Double Precision Register Transfer - 1st operand or 2nd & 3rd operand if not preceded by memory transfer (cache miss) cycle | 1 | 2 | 3 | CP lines DOB nop DOB DAL cdata -- cdata Single Precision Register Transfer - 2nd & 3rd operand if preceded by memory transfer (cache miss) cycle | 1 | 2 | CP lines nop DOB DAL -- cdata Double Precision Register Transfer - 2nd & 3rd operand if preceded by memory transfer (cache miss) cycle | 1 | 2 | 3 | 4 | CP lines nop DOB nop DOB DAL -- cdata -- cdata Single Precision Memory Transfer - longword aligned, cache hit cycle | 1 | 2 | CP lines nop DOB DAL adr cdata Single Precision Memory Transfer - longword aligned, cache miss, ideal memory cycle | 1 | 2 | 3 | 4 | 5 | CP lines nop DOB nop nop nop DAL adr -- data fill -- Single Precision Memory Transfer - longword unaligned, does not cross quadword, ideal memory cycle | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | CP lines nop DOB nop nop nop nop DOB nop DAL adr -- data fill -- adr cdata -- Single Precision Memory Transfer - longword unaligned, crosses quadword, cache misses, ideal memory cycle | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | CP lines nop DOB nop nop nop nop DOB NOP nop nop DAL adr -- data fill -- adr -- data fill -- Double Precision Memory Transfer - quadword aligned, cache hit cycle | 1 | 2 | 3 | 4 | CP lines nop DOB nop DOB DAL adr cdata -- cdata Double Precision Memory Transfer - quadword aligned, cache miss, ideal memory cycle | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | CP lines nop DOB NOP nop nop nop DOB nop DAL adr -- data fill -- adr cdata -- Double Precision Memory Transfer - quadword unaligned, longword aligned, CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 93 INTERFACE 1st longword cache miss, 2nd longword cache hit, ideal memory cycle | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | CP lines nop DOB nop nop nop nop DOB nop DAL adr -- data fill -- adr cdata -- Double Precision Memory Transfer - quadword unaligned, longword aligned, 1st & 2nd longword cache miss, ideal memory cycle | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | CP lines nop DOB nop nop nop nop DOB nop nop nop DAL adr -- data fill -- adr -- data fill -- Double Precision Memory Transfer - longword unaligned (worst case) cycle | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | CP lines nop DOB nop nop nop nop DOB nop nop nop DAL adr -- data fill -- adr -- data fill -- cycle | 11 | 12 | 13 | 14 | CP lines nop DOB nop DOB DAL adr cdata adr cdata 4.4.6.3 Passing Results Back From CFPA - Single Precision Transfers - CFPA ready with results cycle | 1 | 2 | 3 | CP lines rr cc lcpr DAL adr hiz cpd Double Precision Transfers - CFPA ready with two results cycle | 1 | 2 | 3 | 4 | CP lines rr cc cpr lcpr DAL adr hiz cpd cpd Double Precision Transfers - CFPA ready with three results cycle | 1 | 2 | 3 | 4 | 5 | CP lines rr cc cpr cpr lcpr DAL adr hiz cpd cpd cpd CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 94 INTERFACE 4.5 Test Logic The test logic enables test hardware to read internal chip state that is not normally observable on the external pins. It also allows a VLSI chip tester to redefine fifteen pins in order to gain control of internal logic. Some knowledge of the internal organization of the CVAX CPU chip is necessary in order to understand the significance of the test logic output. It is beyond the scope of this specification to describe the internal organization of the chip. For further information, the applicable documents listed in section 1.2 should be consulted. The Test Logic can be conceptually divided into logic that aids observability and logic that controls the test operation. 4.5.1 Observability Logic - The observability logic consists of three parallel-in serial-out test registers, a main data reducer register, logic to parallel load internal signals into these registers, and logic that allows CWB L to be redefined as an output in order to allow the registers to be externally observed. CWB L changes to a test output when TEST H is asserted. The contents of the test registers can be observed using either scan mode or reduce mode. In scan mode, the selected test register is simply serially shifted out to the CWB L pin. In reduce mode, the test registers become linear feedback shift registers and the selected output is serially shifted out to the CWB L pin. The three test registers feed a fourth reducer register known as the main reducer. The main reducer is a linear feedback shift register output can also be serially shifted out to the CWB L pin. CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 95 INTERFACE 4.5.2 Control Logic - The Configuration Register control the operation of the Test Logic. This register selects what is going to drive the CWB L pin (either one of the three test registers or the main reduce), the mode of operation for the test registers (scan or reduce), and if a test broadcast should be forced. 3 2 1 0 +---+---+---+---+ | B | S | | | R | - | SELECT| Configuration Register <3:0> | O | R | | +---+---+---+---+ Bit Function --- -------- 3 force broadcast 0=no broadcast 1=force broadcast 2 Scan/Reduce select 0=reduce 1=scan 1:0 select which register to observe 00=main reducer 01=test register #1 10=test register #2 11=test register #3 When TEST H is negated, the configuration register is reset to 0000 and the assertion of CWB L indicates Clear Write Buffer. 4.5.3 Normal State - The Test Logic is in the 'normal' state when TEST H is negated. No pins are redefined and CWB L indicates when to clear any external write buffers. The configuration latch is cleared. 4.5.4 Test State - 4.5.4.1 Internal MAB - The Test Logic is in the 'test' state when TEST H is asserted. HALT L is now redefined to EXTERNAL H which controls whether the internal control store microaddress bus (MAB) is driven by external pins or the normal internal paths; PWRFL L is redefined to LOAD H which is used to control the parallel loading of the test registers and main reducer register; and CWB L is driving out test state. When EXTERNAL H (HALT L) is negated, MAB is controlled by the normal internal paths. CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 96 INTERFACE 4.5.4.2 External MAB - When TEST H and EXTERNAL H (HALT L) are both asserted, IRQ<1:3> L, CPSTA<0:1> H and CPDAT<0:5> H are redefined to EXTERNAL MAB<10:0> H, respectively; and, IRQ<0> L is redefined to CONFIGURE H. Internal MAB<10:0> is driven by EXTERNAL MAB<10:0> H (IRQ<1:3> L, CPSTA<0:1> H and CPDAT<0:5> H) which are latched at the beginning of each cycle. If CONFIGURE H (IRQ<0> L) is asserted, Configuration Register <3:0> is loaded in the middle of each cycle with CPSTA<0:1> L and CPDAT<1:2> H, respectively. 4.5.4.3 Force Broadcast - If the broadcast bit in the configuration latch is set, DAL<31:0> H are driven with the contents of the internal W bus on every cycle. 4.5.5 Test Registers - The three test registers capture the following information: Test Register Length Information ------------- ------ ----------------------- Register #1 44 MIB<40:0> & UTEST<2:0> Register #2 12 I Box IPLA Register #3 1 Cache refresh address generator 4.5.6 Main Reducer - The main reducer is fed by the outputs of the three test registers. This register only operates in the reduce mode. CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 97 INTERFACE 4.5.7 Test Control Pins Allocation - +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | C | H | P | I | I | I | I | C | C | C | C | C | C | C | C | TEST H = 0 | W | A | W | R | R | R | R | P | P | P | P | P | P | P | P | normal | B | L | R | Q | Q | Q | Q | S | S | D | D | D | D | D | D | operation | | T | F | 0 | 1 | 2 | 3 | T | T | A | A | A | A | A | A | | | | | | | | | A | A | T | T | T | T | T | T | | | | | | | | | 0 | 1 | 0 | 1 | 2 | 3 | 4 | 5 | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | T | E | L | I | I | I | I | C | C | C | C | C | C | C | C | TEST H = 1 | E | X | O | R | R | R | R | P | P | P | P | P | P | P | P | Test State - internal MAB EXTERNAL H = 0 | S | T | A | Q | Q | Q | Q | S | S | D | D | D | D | D | D | CWB L drives test state | T | E | D | 0 | 1 | 2 | 3 | T | T | A | A | A | A | A | A | | O | R | | | | | | A | A | T | T | T | T | T | T | | U | N | | | | | | 0 | 1 | 0 | 1 | 2 | 3 | 4 | 5 | | T | | | | | | | | | | | | | | | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | T | E | L | C | | TEST H = 1 | E | X | O | O | EXTERNAL MAB<0:10> | Test State - external MAB EXTERNAL H = 1 | S | T | A | N | | sampled early in the cycle | T | E | D | F | | CWB L drives test state | O | R | | I | | | U | N | | G | 1 | | T | | | | 0 9 8 7 6 5 4 3 2 1 0 | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | B | S | | | CONFIGURE H = 1 | R | - | | SELECT| Value of these pins are latched | O | R | | | into the Configuration Register +---+---+ +---+---+ in the middle of the cycle if CONFIGURE H = 1 Signal Function ------ -------- EXTERNAL H External/Internal MAB 0 = internal 1 = external LOAD H parallel load scan shift register with scan data. 0 = no load 1 = load CONFIGURE H parallel load configuration latch 0 = do not load Configuration Register from CPSTA<0:1>'CPDAT<1:2> 1 = load Configuration Register CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 98 DC CHARACTERISTICS 5 DC CHARACTERISTICS 5.1 Electrostatic Discharge MINIMUM RATED ELECTROSTATIC DISCHARGE VOLTAGE IS 500 V 5.2 Absolute Maximum Ratings Electrostatic Discharge 500 V Storage Temperature Range -55 C to +125 C Active Temperature Range 0 C to +125 C NOTE Airflow should be provided so that the active temperature does not exceed 100 deg C. Supply Voltage -0.5 V to +7.0 V Input or Output Voltage Applied -1 V to +7.0 V 5.3 Electrical Characteristics Specified Temperature Range 0 C to +70 C Specified Supply Voltage Range +4.75 V to +5.25 V Test Conditions Temperature = +70 C Vss = 0 V Vcc = +4.75 V (except as noted) Symbol Parameter Min Max Units Test Condition ------ --------- --- --- ----- -------------- Vih High level input 2.0 V voltage (TTL) Vil Low level input 0.8 V voltage (TTL) Vihe High level input 2.4 V voltage (TTL edge triggered inputs) Vohm High level output 90% Vdd V voltage (MOS) Volm Low level output 10% Vdd V voltage (MOS) Vihm High level input 70% Vdd V CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 99 DC CHARACTERISTICS voltage (MOS) Vilm Low level input 30% Vdd V voltage (MOS) Voh High level output 2.4 V Ioh = - 400 uA voltage Vol Low level output 0.4 V Iol = 2.0 mA (all pins except DALs and DBE L) voltage Iol = 3.0 mA (DALs) Iol = 4.0 mA (DBE) Iil Input leakage -10 10 uA 0 < Vin < 5.25 V current Iol Output leakage -100 100 uA Vin = 0.4 V current Icc Active supply current 300 mA Iout = 0, Ta = 0 C Cin Input capacitance 5 pF Cout Output capacitance 10 pF Cio Input/Output capacitance 10 pf CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 100 DC CHARACTERISTICS 5.4 Signal Summary Signal Signal Pin Name Type Number Applicable Tests ------ ------ ------ ---------------- V V V | V V | I I | V V | V V i i i | o o | i o | i i | o o h h l | h l | l l | h l | h l e | | | m m | m m ---------------------------------------------------------------+---------+----------+--------+------- DAL<31> H IO 84 X X | X X | X X | | DAL<30> H IO 83 X X | X X | X X | | ---------------------------------------------------------------+---------+----------+--------+------- DAL<29> H IO 82 X X | X X | X X | | DAL<28> H IO 81 X X | X X | X X | | ---------------------------------------------------------------+---------+----------+--------+------- DAL<27> H IO 80 X X | X X | X X | | DAL<26> H IO 79 X X | X X | X X | | ---------------------------------------------------------------+---------+----------+--------+------- DAL<25> H IO 78 X X | X X | X X | | DAL<24> H IO 74 X X | X X | X X | | ---------------------------------------------------------------+---------+----------+--------+------- DAL<23> H IO 73 X X | X X | X X | | DAL<22> H IO 72 X X | X X | X X | | ---------------------------------------------------------------+---------+----------+--------+------- DAL<21> H IO 71 X X | X X | X X | | DAL<20> H IO 70 X X | X X | X X | | ---------------------------------------------------------------+---------+----------+--------+------- DAL<19> H IO 69 X X | X X | X X | | DAL<18> H IO 68 X X | X X | X X | | ---------------------------------------------------------------+---------+----------+--------+------- DAL<17> H IO 67 X X | X X | X X | | DAL<16> H IO 66 X X | X X | X X | | ---------------------------------------------------------------+---------+----------+--------+------- DAL<15> H IO 65 X X | X X | X X | | DAL<14> H IO 64 X X | X X | X X | | ---------------------------------------------------------------+---------+----------+--------+------- DAL<13> H IO 63 X X | X X | X X | | DAL<12> H IO 62 X X | X X | X X | | ---------------------------------------------------------------+---------+----------+--------+------- DAL<11> H IO 61 X X | X X | X X | | DAL<10> H IO 60 X X | X X | X X | | ---------------------------------------------------------------+---------+----------+--------+------- DAL<09> H IO 59 X X | X X | X X | | DAL<08> H IO 58 X X | X X | X X | | ---------------------------------------------------------------+---------+----------+--------+------- DAL<07> H IO 57 X X | X X | X X | | DAL<06> H IO 56 X X | X X | X X | | ---------------------------------------------------------------+---------+----------+--------+------- DAL<05> H IO 55 X X | X X | X X | | DAL<04> H IO 54 X X | X X | X X | | ---------------------------------------------------------------+---------+----------+--------+------- CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 101 DC CHARACTERISTICS Signal Signal Pin Name Type Number Applicable Tests ------ ------ ------ ---------------- V V V | V V | I I | V V | V V i i i | o o | i o | i i | o o h h l | h l | l l | h l | h l e | | | m m | m m ---------------------------------------------------------------+---------+----------+--------+------- DAL<03> H IO 50 X X | X X | X X | | DAL<02> H IO 49 X X | X X | X X | | ---------------------------------------------------------------+---------+----------+--------+------- DAL<01> H IO 48 X X | X X | X X | | DAL<00> H IO 47 X X | X X | X X | | ---------------------------------------------------------------+---------+----------+--------+------- CS/DP<3> H IO 39 X X | X X | X X | | CS/DP<2> H IO 40 X X | X X | X X | | ---------------------------------------------------------------+---------+----------+--------+------- CS/DP<1> H IO 41 X X | X X | X X | | CS/DP<0> H IO 42 X X | X X | X X | | ---------------------------------------------------------------+---------+----------+--------+------- DPE L IO 38 X X | X X | X X | | AS L IO 30 X X | X X | X X | | ---------------------------------------------------------------+---------+----------+--------+------- CPDAT<5> H IO 3 | | | X X | X X CPDAT<4> H IO 4 | | | X X | X X ---------------------------------------------------------------+---------+----------+--------+------- CPDAT<3> H IO 5 | | | X X | X X CPDAT<2> H IO 6 | | | X X | X X ---------------------------------------------------------------+---------+----------+--------+------- CPDAT<1> H IO 7 | | | X X | X X CPDAT<0> H IO 8 | | | X X | X X ---------------------------------------------------------------+---------+----------+--------+------- CPSTA<1> H IO 9 | | | X X | X X CPSTA<0> H IO 10 | | | X X | X X ---------------------------------------------------------------+---------+----------+--------+------- DS L O 29 | X X | X | | BM<3> L O 43 | X X | X | | ---------------------------------------------------------------+---------+----------+--------+------- BM<2> L O 44 | X X | X | | BM<1> L O 45 | X X | X | | ---------------------------------------------------------------+---------+----------+--------+------- BM<0> L O 46 | X X | X | | WR L O 32 | X X | X | | ---------------------------------------------------------------+---------+----------+--------+------- DBE L O 31 | X X | X | | DMG L O 25 | X X | X | | ---------------------------------------------------------------+---------+----------+--------+------- RDY L I 27 X X | | X | | ERR L I 28 X X | | X | | ---------------------------------------------------------------+---------+----------+--------+------- RESET L I 35 X X | | X | | HALT L I 19 X X | | X | | ---------------------------------------------------------------+---------+----------+--------+------- CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 102 DC CHARACTERISTICS Signal Signal Pin Name Type Number Applicable Tests ------ ------ ------ ---------------- V V V | V V | I I | V V | V V i i i | o o | i o | i i | o o h h l | h l | l l | h l | h l e | | | m m | m m ---------------------------------------------------------------+---------+----------+--------+------- IRQ<3> L I 14 X X | | X | | IRQ<2> L I 13 X X | | X | | ---------------------------------------------------------------+---------+----------+--------+------- IRQ<1> L I 12 X X | | X | | IRQ<0> L I 11 X X | | X | | ---------------------------------------------------------------+---------+----------+--------+------- PWRFL L I 18 X X | | X | | CRD L I 16 X X | | X | | ---------------------------------------------------------------+---------+----------+--------+------- INTTIM L I 15 X X | | X | | DMR L I 26 X X | | X | | ---------------------------------------------------------------+---------+----------+--------+------- CCTL L I 24 X X | | X | | MEMERR L I 17 X X | | X | | ---------------------------------------------------------------+---------+----------+--------+------- CLKA L I 34 | | X | X X | CLKB L I 33 | | X | X X | ---------------------------------------------------------------+---------+----------+--------+------- * TEST H/Vss I 20 X X | | | | CWB L O 23 | X X | X | | ---------------------------------------------------------------+---------+----------+--------+------- * High signals test mode. When not in test mode, this pin must be connected to Vss. CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 103 AC CHARACTERISTICS 6 AC CHARACTERISTICS Test Conditions: (except as noted) Temperature = +70 C Vss = 0 V Vdd = +4.75V Cload = 130pF (except CPDAT and CPSTA) AC measurements are made from Vilm/Vihm on MOS inputs, Volm/Volh on MOS outputs, Vil/Vih on TTL inputs, and Vol/Voh on TTL outputs. MOS inputs are driven to Volm/Vohm and TTL inputs are driven to Vol/Voh on TTL inputs. 6.1 80nS Input Requirements (21-24674-16) Symbol Parameter Min Max Units Remarks ------- ---------- ---- ---- ----- -------- Tclke External clock edge rate 0 8 ns Tcycle External clock cycle 40 200 ns Tclkh External clock high Tcyclem/2 - Tclke(max) 100 ns Tclkl External clock low Tcyclem/2 - Tclke(max) 100 ns Tclkdly CLKA to CLKB delay Tcycle/2 - 1 Tcycle/2 + 1 ns nominal values 19 21 ns Tresetw Reset input width 10*Tcycle ns nominal values 400 ns Tresets Reset input setup prior to P1 15 Tcycle-3 ns nominal values 37 ns Tsyns Asynchronous input setup 12 ns CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 104 AC CHARACTERISTICS Tsynh Asynchronous input hold 12 ns Tsynr Asynchronous input rise time 12 ns Tsynf Asynchronous input fall time 12 ns Tds DAL setup 20 ns Tdps parity setup 16 ns Tdh DAL hold 4 ns Tdz DAL tri-state Tcycle ns nominal value 40 ns Tsws RDY L & ERR L assertion setup 12 ns Tswh RDY L & ERR L sample window hold 4 ns Tswlmax RDY L & ERR L maximum assertion time 45 ns Tswds RDY L & ERR L negation setup Tclkh ns nominal value 20 ns Tcps Coprocessor line setup 18 ns Cload = 50pF Tcph Coprocessor line hold 18 Cload = 50pF Tdsdly DS L delay from receiving DMG L 3*Tcycle ns nominal value 120 ns Tasdly AS L delay from asserting CCTL L during cache 2*Tcycle-Tclkh+ invalidates Tsyns-Tcctladrs ns nominal value 56 ns Tcctlw CCTL width during cache invalidates Tsyns+Tsynh ns nominal value 24 ns Tcctlcyc CCTL cycle time during 6*Tcycle+ CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 105 AC CHARACTERISTICS octaword invalidates Tsyns+Tsynh ns nominal value 264 ns Tcctladrs AS L set up during cache invalidates 16 ns Taswq AS L width during 4*Tcycle+ quadword invalidates Tcctladrs+Tash+ Tasdly(max)-Tasdly ns nominal value 200 ns Tasdly=Tasdly(max) Taswo AS L width during Tcctlcyc-2*Tasdly+ octaword invalidates Taswq+Tasdly(max) ns nominal value 408 ns Tasdly=Tasdly(max) Tash AS L hold during cache invalidates Tcycle/2 + 4 ns nominal value 24 ns Tasadrs DAL setup 16 ns during cache invalidates Tasadrh DAL hold 16 ns during cache invalidates Tth test input hold 5 ns Tts test input setup 10 ns 6.2 80nS Output Responses (21-24674-16) Symbol Parameter Min Max Units Remarks ------ ---------- ---- ---- ----- -------- Tsd General strobe assertion delay 0 18 ns Tsid strobe negation delay 0 18 ns Tasd AS strobe assertion delay 0 13.5 ns Tasid AS strobe negation delay 0 18 ns Tdsd DS strobe assertion delay 0 18 ns Tdsid DS strobe negation CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 106 AC CHARACTERISTICS delay 0 16 ns Tdmgsd DMG strobe assertion delay 0 18 ns Tdmgsid DMG strobe negation delay 0 18 ns Tshlz Strobe tri-state delay 0 18 ns Tszhl Strobe active drive delay 0 18 ns Tdalhlz DAL tri-state delay 0 18 ns Tdalzhl DAL active drive delay 0 18 ns Tdald DAL drive 0 18 ns Tdalh DAL hold 4.5 ns Tparityd DP drive 0 31.5 ns Tparityh DP hold 4.5 ns Tbmh BM and WR hold 0 ns Tcpd Coprocessor line drive 0 18 ns Cload is 50pF Tcpdh Coprocessor line hold 0 ns Cload is 50pF Tcphlz Coprocessor tri-state delay 0 18 ns Tinitasd First assertion of AS L after RESET L 20*Tcycle ns nominal value 800 ns Ttestd CWB L drive 0 29 ns Ttesth CWB L hold 0 ns Tresetd Strobe inactive delay from reset 0 400 ns Tresetz Bus tristate time from reset 0 22.5 ns Tresetdly Output drive from reset negation 7*Tcycle 7*Tcycle+18 ns CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 107 AC CHARACTERISTICS nominal value 280 298 ns 6.3 60nS Input Requirements (21-24674-15) Symbol Parameter Min Max Units Remarks ------- ---------- ---- ---- ----- -------- Tclke External clock edge rate 0 6 ns Tcycle External clock cycle 30 200 ns Tclkh External clock high Tcyclem/2 - Tclke(max) 100 ns Tclkl External clock low Tcyclem/2 - Tclke(max) 100 ns Tclkdly CLKA to CLKB delay Tcycle/2 - 1 Tcycle/2 + 1 ns nominal values 14 16 ns Tresetw Reset input width 10*Tcycle ns nominal values 300 ns Tresets Reset input setup prior to P1 8 Tcycle-3 ns nominal values 27 ns Tsyns Asynchronous input setup 9 ns Tsynh Asynchronous input hold 9 ns Tsynr Asynchronous input rise time 9 ns Tsynf Asynchronous input fall time 9 ns Tds DAL setup 15 ns Tdps parity setup 12 ns Tdh DAL hold (note 1) 3 ns CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 108 AC CHARACTERISTICS Tdz DAL tri-state Tcycle ns nominal value 30 ns Tsws RDY L & ERR L assertion setup 9 ns Tswh RDY L & ERR L sample window hold 3 ns Tswlmax RDY L & ERR L maximum assertion time 35 ns Tswds RDY L & ERR L negation setup Tclkh ns nominal value 15 ns Tcps Coprocessor line setup 14 ns Cload = 50pF Tcph Coprocessor line hold 14 Cload = 50pF Tdsdly DS L delay from receiving DMG L 3*Tcycle ns nominal value 90 ns Tasdly AS L delay from asserting CCTL L during cache 2*Tcycle-Tclkh+ invalidates Tsyns-Tcctladrs ns nominal value 42 ns Tcctlw CCTL width during cache invalidates Tsyns+Tsynh ns nominal value 18 ns Tcctlcyc CCTL cycle time during 6*Tcycle+ octaword invalidates Tsyns+Tsynh ns nominal value 198 ns Tcctladrs AS L set up during cache invalidates 12 ns Taswq AS L width during 4*Tcycle+ quadword invalidates Tcctladrs+Tash+ Tasdly(max)-Tasdly ns nominal value 150 ns Tasdly=Tasdly(max) Taswo AS L width during Tcctlcyc-2*Tasdly+ octaword invalidates Taswq+Tasdly(max) ns CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 109 AC CHARACTERISTICS nominal value 306 ns Tasdly=Tasdly(max) Tash AS L hold during cache invalidates Tcycle/2 + 3 ns nominal value 18 ns Tasadrs DAL setup 12 ns during cache invalidates Tasadrh DAL hold 12 ns during cache invalidates Tth test input hold 5 ns Tts test input setup 10 ns Note 1 : CVAX will stop actively driving the DALs Tdh after the beginning of phase_1 and not actively drive the DALs again till the beginning of phase_3. 6.4 60nS Output Responses (21-24674-15) Symbol Parameter Min Max Units Remarks ------ ---------- ---- ---- ----- -------- Tsd General strobe assertion delay 0 16 ns Tsid strobe negation delay 0 16 ns Tasd AS strobe assertion delay 0 12 ns Tasid AS strobe negation delay 0 16 ns Tdsd DS strobe assertion delay 0 16 ns Tdsid DS strobe negation delay 0 14.5 ns Tdmgsd DMG strobe assertion delay 0 16 ns Tdmgsid DMG strobe negation delay 0 16 ns Tshlz Strobe tri-state delay 0 16 ns Tszhl Strobe active drive CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 110 AC CHARACTERISTICS delay 0 16 ns Tdalhlz DAL tri-state delay 0 16 ns Tdalzhl DAL active drive delay 0 16 ns Tdald DAL drive 0 16 ns Tdalh DAL hold 4 ns Tparityd DP drive 0 23 ns Tparityh DP hold 4 ns Tbmh BM and WR hold 0 ns Tcpd Coprocessor line drive 0 16 ns Cload is 50pF Tcpdh Coprocessor line hold 0 ns Cload is 50pF Tcphlz Coprocessor tri-state delay 0 16 ns Tinitasd First assertion of AS L after RESET L 20*Tcycle ns nominal value 600 ns Tdper Release of DPE by external logic 0 ns prior to CVAX driving DPE high Ttestd CWB L drive 0 25 ns Ttesth CWB L hold 0 ns Tresetd Strobe inactive delay from reset 0 300 ns Tresetz Bus tristate time from reset 0 20 ns Tresetdly Output drive from reset negation 7*Tcycle 7*Tcycle+16 ns nominal value 210 226 ns CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 111 TIMING DIAGRAMS 7 TIMING DIAGRAMS 7.1 Clock Timing Requirements ____ ____ ____ ____ ____ ____ ____ CLKA 90% /| \ /| |\ / \ /| |\ / \ / \ / \ / | \ / | | \ / \ / | | \ / \ / \ / \ 10% / | \____/ | | \____/ \____/ | | \____/ \____/ \____/ \____ | | | | | | | | | | | --->| |<---Tclke | | --->| |<---Tclkl --->| |<--Tclke | --->| |<---Tclkh | | |<---Tcycle-->| | --->| |<---Tclkdly | |___ ____ ____ ____ ____ ____ ____ CLKB 90% \ /| \ /| |\ / \ /| |\ / \ / \ / \ / | \ / | | \ / \ / | | \ / \ / \ / 10% \____/ | \____/ | | \____/ \____/ | | \____/ \____/ \____/ | | | | | | | | | | | --->| |<---Tclke -->| |<---Tclkh -->| |<---Tclkl --->| |<--Tclke | | | |<---Tcycle-->| CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 112 TIMING DIAGRAMS 7.2 Initialization P1 P3 P1 P3 ____ ____ ____ ____ ____ ____ ____ CLKA 90% / \ / \ / \ /| \ / \ / \ / \ / \ / \ / \ / | \ / \ / \ / \ 10% / \____/ \ ... / \____/ | \____/ \ ... / \____/ \____ | --->| |<---Tresets | | |<---------Tresetw------------>| | | ''''''''\ | | /''''''''''''''''''''''' ... '''''''''''''''''''''''''''' RESET L \,,,,,,,,,,,,,, ... ,,,,,,,,,,,,,/| | | | | |<-----------Tinitasd-------------->| -->| |<--Tresetd | | | | | | AS L '''''''''''''''''''''''' ... '''''''''''''''''''''''''''''''''''''''...'''''''''\ | ,,,,,,,,,,,,,,,/ | \,,,,,,,,,,,,,,,,,, | | -->| |<--Tresetd | | | | DS L '''''''''''''''''''''''' ... '''''''''''''''''''''''''''''''''''''''...''''''''''''''''\ DBE L ,,,,,,,,,,,,,,,/ | \,,,,,,,,,,, DMG L | | CWB L | | | | -->| |<--Tresetz |<----Tresetdly----->| WR L | | | | DAL<31:0> H '''''''''''''''''''\| | /'''''''''''''''''''''''''''''''' BM<3:0> H >--- ... ---------------------------- ... ----< CS/DP<3:0> H ,,,,,,,,,,,,,,,,,,,/ | \,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, DPE L | | | |<----Tresetdly----->| | | -->| |<--Tresetd | | | | CPSTA<0> H ''''''''''''''''''''/''' ... '''''''''''''''''''''''''''' ... '''\ | ,,,,,,,,,,,,,,,,,,,/ \,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, | | -->| |<--Tresetd | CPDAT<5:0> H '''''''''''''''''''\| CPSTA<1> H ,,,,,,,,,,,,,,,,,,,,\,,, ... ,,,,,,,,,,,,,,,,,,,,,,,,,,,, ... ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 113 TIMING DIAGRAMS 7.3 CWB L And TEST L Timing Internal phase P3 P1 P3 P1 P3 P1 P3 ____ ____ ____ ____ ____ ____ ____ CLKA 90% /| \ / \ / \ /| \ /| \ / \ / \ / | \ / \ / \ / | \ / | \ / \ / \ 10% / | \____/ \____/ \____/ | \____/ | \____/ \____/ \____ | | | Internal phase | P4 P2 P4 | P2 | P4 P2 P4 | ____ ____ ____ | ____ | ____ ____ ____ CLKB 90% \ | / \ / \ / \ | /| \ | /| \ /| \ / \ | / \ / \ / \ | / | \ | / | \ / | \ / 10% \____/ \____/ \____/ \____/ | \____/ | \____/ | \____/ | | | | | | -->| |<--Ttestd | | -->| |<---Ttestd | | | | | | | | | -->| |<--Ttesth | | -->| |<--Ttesth | | | | | | | | | | CWB L '''''''\ /'''''''''''''''''''''''''\ /'''''''''''''''''''''''\ /'''''''''''''''''''''''''''\ /'''' x clear write buf x clear write buf x test state x ,,,,,,,/ \,,,,,,,,,,,,,,,,,,,,,,,,,/ \,,,,,,,,,,,,,,,,,,,,,,,/ \,,,,,,,,,,,,,,,,,,,,,,,,,,,/ \,,,, | | | | | | -->| |<--Tts| | | | | | | | | -->| |<--Tth | | | | | | | | | TEST H ////''''''''''''''''''''''''''''''''''''''''''''''' ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,//// | | | | | | | | | -->| |<--Tts| | | | | | -->| |<--Tth | | | | | | IRQ<3:0> L ''''''''''''''''''''''''''''''''''''''''''''''''''''''\\//'''''''''''''''''''''''''''''''''''''''' HALT L normal inputs xx test inputs PWRF L ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,//\\,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, | | | -->| |<--Tth | | -->| |<--Tts | | | ''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''\\//'''''''''''''''''''\\//'''''''''''' CPSTA<1:0> H normal inputs xx test inputs xx test inputs CPDAT<5:0> H ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,//\\,,,,,,,,,,,,,,,,,,,//\\,,,,,,,,,,,, CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 114 TIMING DIAGRAMS 7.4 External Interrupt Timing Internal phase P1 P3 P1 ____ ____ ____ CLKA 90% / \ / \ / \ / \ / \ / \ 10% / \____/ \____/ \ Internal phase P2 P4 ____ ____ CLKB 90% \ / |\ / \ / \ / | \ / \ / 10% \____/ | \____/ \____/ | -->| |<--Tsyns | | | -->| |<--Tsynh | | | IRQ<3:0> L '''\ | | | /''''''''''''''' | \,,,,,,,,,,,,,,,,/ | | | | | | -->| |<---Tsynf -->| |<--Tsynr | -->| |<--Tsyns | | MEMERR L | CRD L '''\ | /''''''''''''''' PWRFL L | \,,,,,,,,,,,,,,,,/ | INTTIM L | | | | HALT L -->| |<--Tsynf -->| |<--Tsynr | | |<----Tcctlw---->| IRQ<3:0> L are level sensitive and must remain asserted for a setup (Tsyns) and hold time (Tsynh) around the end of P2 in order to guarantee recognition. Low going pulses that occur outside the setup and hold window will not be recognized. MEMERR L, CRD L, PWRFL L, INTTIM L, and HALT L are edge sensitive. The assertion transition must occur a setup time (Tsyns) before the end of P2 in order to guarantee recognition at a particular point; otherwise, recognition is delayed one cycle. CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 115 TIMING DIAGRAMS 7.5 External DMA Timing Internal phase P3 P1 P3 P3 P1 P3 P1 P3 P1 ___ ___ ___ ___ ___ ___ ___ ___ ___ CLKA 90% / \ / \ / /| \ / \ / \ / \ /| \ / \ / \ / \ / / | \ / \ / \ / \ / | \ / \ 10% / \___/ \___/ ... _/ | \_ ... _/ \___/ \___/ \___/ | \___/ | | Internal phase P4 P2 | P4 P4 P2 P4 P2 | P4 ___ ___ ... _ | _ ... _ ___ ___ ___ | ___ CLKB 90% \ / |\ / \ \ | / |\ / \ / \ / \ | / \ \ / | \ / \ \ | / | \ / \ / \ / \ | / \ / 10% \__/ | \___/ \___ \___/ | \___/ \___/ \___/ \___/ \___/ | | | | -->| |<--Tsyns | -->| |<--Tsyns | | | | | | | | ->| |<--Tsynh | | -->| |<--Tsynh | | | | | | | DMR L '''\ | | | /'''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''' | \,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,/ | | | | | | | | -->| |<--Tsynf | -->| |<--Tsynr | | | -->| |<--Tdmgsd -->| |<--Tdmgsid | | | | DMG L '''''''''''''''''''''''''''''''''''''''''''''''\ | | /''''''''''' | \,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,/ | | | | |<------Tdsdly------>| | | ,,,,,,,,,,,,,,, | ,,,, DS L (from DMA) ____________________________________________________/ \ | / \___________ | \,,,,,,,,,,,,,,,,,,/ | DS L (from CVAX CPU) | | AS L -->| |<--Tshlz -->| |<--Tszhl DBE L | | | | DPE L '''''''''''''''''''''''''''''''''''''''''''\_____________________________________________________/'''''''''' BM L | | WR L -->| |<--Tdalhlz -->| |<---Tdalzhl | | '''''''''''''''''''''''''''''''''''''''''\ | /''''''''''' DAL<31:0> H >----------------------------------------------------< CS/DP<3:0> L ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,/ \,,,,,,,,,,, Tsyns and Tsynh are the setup and hold times needed at a synchronizer input to guarantee that the signal is recognized as expected. DMG L is asserted on P3 when DMR L is asserted seven phases earlier and no CPU IO cycle has started. DMG L is negated on P3 when DMR L is negated seven phases earlier. CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 116 TIMING DIAGRAMS 7.6 Quadword Cache Invalidate Cycle Internal phase P3 P1 P3 P3 P1 P3 P1 P3 ____ ____ ____ ____ ____ ____ ____ _ CLKA 90% / \ / \ / \ / \ / \ / \ / \ / / \ / \ / \ / \ / \ / \ / \ / 10% / \____/ \____/ \_ ... _/ \____/ \____/ \____/ \____/ two cycle Internal phase P4 P2 P4 delay P4 P2 P4 P2 ____ ____ ____ ____ ____ ____ _____ CLKB 90% \ / |\ / \ /| \ /| \ / \ / \ / \ \ / | \ / \ / | \ / | \ / \ / \ / \ 10% \____/ | \____/ \____/ | \_ ... _/ | \____/ \____/ \____/ \ | | | -->| |<--Tsyns | | | | | CCTL L ''''\ | /''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''' \,,,,,,,,,,,,,,,,,,,,,,/ | | | | | | |<-------Tcctlw----->| | | | | | | -->| |<--Tcctladrs | | | | |<---------Tasdly-------->| -->| |<-- Tash | | AS L ''''''''''''''''''''''''''''''\ | | /''''''''''''''''''''''''''''''''''''''''' | \,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,/ | | | | |<-----------Taswq---------->| | -->| |<--Tasadrs | | | -->| |<--Tasadrh | | | ''''''''''''''''''''\ /'''''''''''''\ /'''''''''''''''''''''''''''''''''''''\ /'''''''''''''''''''''''''' DAL<31:0> H x DMA address x x next DMA address ,,,,,,,,,,,,,,,,,,,,/ \,,,,,,,,,,,,,/ \,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,/ \,,,,,,,,,,,,,,,,,,,,,,,,,, Tsyns and Tsynh are the setup and hold times needed at a synchronizer input to guarantee that the signal is recognized as expected. Tcctladrs is measured from the P4 that follows recognition of CCTL L. Tash is measured from the third P4 that follows recognition of CCTL L. CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 117 TIMING DIAGRAMS 7.7 Octaword Cache Invalidate Cycle Internal phase P3 P1 P3 P3 P1 P1 P3 P3 ___ ___ ___ ___ ___ ___ ___ ___ CLKA 90% / \ / \ / \ / \ / \ / \ / \ / \ / / \ / \ / \ / \ / \ / \ / \ / \ / 10% / \___/ \___/ \_ .. _/ \___/ \_ .. _/ \___/ \_ .. _/ \___/ Internal phase P4 P2 P4 P4 P4 P2 P4 two P4 ___ ___ ___ ___ ___ ___ ___ cycle ___ CLKB 90% \ / |\ / \ /| \ / \ / |\ / \ / \ delay /| \ \ / | \ / \ / | \ / \ / | \ / \ / \ / | \ 10% \___/ | \___/ \___/ | \_ .. _/ \_ .. _/ | \___/ \___/ \_ .. _/ | \ | | | | -->| |<--Tsyns | -->| |<--Tsyns | | | | | | | | -->| |<--Tsynh | | -->| |<--Tsynh | | | | | | | CCTL L ''''\ | | /'''''''''''''''''''''''''''''''''\ | | /''''''''''''''''''''''''''''' \,,,,,,,,,,,,,,,,,/ \,,,,,,,,,,,,,,,,,/ | | | | | | | |<---Tcctlw---->| | |<---Tcctlw---->| | | | | | |<---------------------------Tcctlcyc---------------->| | | | | |<---Tasdly--------->| | | | | | -->| |<--Tcctladrs Tash-->| |<-- | | AS L '''''''''''''''''''''''''\ | | /' | \,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,/ | | | | |<-----------------------------------Taswo---------------------------------->| | -->| |<--Tasadrs | | | -->| |<--Tasadrh | | | ''''''''''''''''\ /'''''''''''\ /''''''''''''''''''''''''''''''''''''''''''''''''''''''\ /'''''''''''''''''' DAL<31:0> H x DMA address x x next DMA address ,,,,,,,,,,,,,,,,/ \,,,,,,,,,,,/ \,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,/ \,,,,,,,,,,,,,,,,,, Tsyns and Tsynh are the setup and hold times needed at a synchronizer input to guarantee that the signal is recognized as expected. Tcctladrs is measured from the P4 that follows recognition of the first CCTL L. Tash is measured from the third P4 that follows recognition of the second CCTL. CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 118 TIMING DIAGRAMS 7.8 Single Transfer CPU Read Cycle, Interrupt Acknowledge Cycle Internal phase P1 P3 P1 P3 P1 P3 P1 ____ ____ ____ ____ ____ ____ ____ CLKA 90% / \ /| \ /| \ /| \ /| \ / \ / \ / \ / | \ / | \ / | \ / | \ / \ / \ 10% / \____/ | \____/ | \____/ | \____/ | \____/ \____/ \____ | | | | Internal phase P2 | P4 | P2 | P4 | P2 P4 P2 ____ | ____ | ____ | ____ | ____ ____ ____ CLKB 90% \ / \ | /| \ | /| \ | / \ | /| \ / \ / \ / \ | / | \ | / | \ | / \ | / | \ / \ / 10% \____/ \____/ | \____/ | \____/ \____/ | \____/ \____/ | | | | | | | -->| ||<---Tdald | | -->| |<--Tdz | || | | | | | | | || | -->| |<--Tdalh -->| |<---Tds | || | | | | | | | | | || | -->| | |<--Tdalhlz | -->| |<--Tdh | || | | | | | | | | | | ''''''''''\ | /'''''''''''''''''''\ | | /'''''''\ | | /'''''''''''''''\ DAL<31:00> >-------< address >-----------< data >---------------< >------ ,,,,,,,,,,/ | \,,,,,,,,,,,,,,,,,,,/ | \,,,,,,,/ | \,,,,,,,,,,,,,,,/ | | | | | | | | | | -->| |<--Tdalh -->| |<---Tdps | | | | | | | | | -->| ||<--Tdald -->| | |<--Tdalhlz | -->| |<--Tdh | || | | | | | | | | | ''''''''''''''''''''''''''''''''''''''''\ | | /''\ /'''''''\ /''''''\ /'''''''''''''''''''''''''' DPE L / | | >------< x x >---< ,,,,,,,,,,,,,,,,,,,,,,,/| | | | \,,/ \,,,,,,,/ \,,,,,,/ | | | | | | | | | | | | | -->| |<---Tdps | | | | | | | | | | | | | | -->| |<--Tdh | | | | | | | | | ''''''''''''''''''''''''''''''''''''''''''''''''''''\ /'''''''\ /''''''''''''''''''''''''''''''''''''''' CCTL L x x ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,/ \,,,,,,,/ \,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, | | | | | | | | | | -->| |<--Tdalh -->| |<--Tdps -->| | |<--Tsd | | | | | | | | | | -->| | |<--Tdalhlz | -->| |<--Tdh | | | | | | | | | | | | ''''''''''\ | /''''\ /''''''''''''\ | | /''\ /'''''''\ /''''''\ /''''''''''''''''''\ CS/DP<3:0> >-------< x CS >------< x DP x >---< >------ ,,,,,,,,,,/ | \,,,,/ \,,,,,,,,,,,,/ | \,,/ \,,,,,,,/ \,,,,,,/ \,,,,,,,,,,,,,,,,,,/ | | | | | | | CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 119 TIMING DIAGRAMS | | -->| |<--Tasd | | -->| |<--Tasid | | | | | | | | | | | | | | | | AS L ''''''''''''''''''''''''''''''''''\ | | | | | /'''''''''''''''''''''''''''''''''' | | \,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,/ | | | | | | | | | -->| |<---Tdsd | | | | | | | | | | | | | -->| |<--Tdsid | | | | | | | | DS L '''''''''''''''''''''''''''''''''''''''''''''''''\ | | /'''''''''''''''''''''''''''''''''' | | | | \,,,,,,,,,,,,/ | | | | | | | | | | | | | | | -->| |<--Tsd | -->| |<--Tsid | | | | | | | DBE L '''''''''''''''''''''''''''''''''''''''''\ | | | /'''''''''''''''''''''''''''''''''' | | | \,,,,,,,,,,,,,,,,,,,,,,,,,/ | | | | | | | | | | | -->| |<--Tsd -->| |<--Tbmh | | | | | | BM<3:0> L ''''''''''''''''''''''''''''''\ /''''''''''''''\ /''''''''''''''''''''''''''''''''''''\ /''''''''''''''' x Valid BM x x ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,/ \,,,,,,,,,,,,,,/ \,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,/ \,,,,,,,,,,,,,,, | | | -->| |<--Tsd -->| |<--Tbmh | | | | WR L '''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''' / \ ,,,,,,,,,,,,,,,,,,,,,/ \,,,, -->| |<--Tsws ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, | | -->| | |<--Tswds | | | | | -->| |<--Tswh | | | | | | -->| | |<--Tswlmax | | | | RDY L ''''''''''''''''''''''''''''''''''''''''''''''''''\ | | /''''''''''''''''''''''''''''''''''''' ERR L \,,,,,,,,,,,,,/ CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 120 TIMING DIAGRAMS Ready slip timing: RDY L and ERR L are sampled coincident with data at T200. If either or both are asserted, the microcycle finishes up as shown. If neither is asserted, the chip strobes (AS L, DS L, DBE L, etc.) remain unchanged and P1 following P4 are restarted. Thus the granularity for RDY and ERR L slips is two clock cycles. Only a high to low (assertion) transition is allowed on RDYL and ERRL during a P4 that is part of a sample window. A low to high transition on RDYL and ERRL during this time will cause unpredictable results! Therefore, RDYL and ERRL must be negated (high) coming into a P4 that is part of a sample window if the intent is to have the CVAX CPU and CFPA see these signals negated. Interfacing note: RDYL and ERRL may be asserted coming into a P4 if they are to be asserted for the sample window; DAL<31:0> and CS/DP<3:0> L are three-stated on P2 of the address part of this cycle. CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 121 TIMING DIAGRAMS 7.9 Multiple Transfer CPU Read Cycle Internal phase P1 P3 P1 P3 P1 P3 P1 ____ ____ ____ ____ ____ ____ ____ CLKA 90% / \ /| \ /| \ /| \ /| \ /| \ /| \ / \ / | \ / | \ / | \ / | \ / | \ / | \ 10% / \____/ | \____/ | \____/ | \____/ | \____/ | \____/ | \____ | | | | | | | | | | | | Internal phase P2 | P4 | P2 | P4 | P2 | P4 | P2 ____ | ____ | ____ | ____ | ____ | ____ | ____ CLKB 90% \ / \ | /| \ | /| \ | / \ | / \ | / \ | /| \ / \ | / | \ | / | \ | / \ | / \ | / \ | / | 10% \____/ \____/ | \____/ | \____/ \____/ \____/ \____/ | | | | | | | | | | -->| ||<---Tdald | | | | -->| |<--Tdz | || | | | | | | | | | || | -->| |<--Tdalh -->| |<---Tds | -->| |<---Tds | || | | | | | | | | | | | | || | -->| | |<--Tdalhlz | -->| |<--Tdh | | -->| |<--Tdh | || | | | | | | | | | | | | | | '''''''''\ | /'''''''''''''''''''\ | | /'''''''\ /'''''''''''''''\ /'''''''\ | | /''' DAL<31:00> >--------< address >-----------< data 1 x x data 2 >------< ,,,,,,,,,/ | \,,,,,,,,,,,,,,,,,,,/ | \,,,,,,,/ \,,,,,,,,,,,,,,,/ \,,,,,,,/ | \,,, | | | | | | | | | | | | -->| |<--Tdalh -->| |<---Tdps | -->| |<---Tdps | | | | | | | | | | | | -->| ||<--Tdald -->| | |<--Tdalhlz | -->| |<--Tdh | | -->| |<--Tdh | || | | | | | | | | | | | | | ''''''''''''''''''''''''''''''''''''''''\ | | /''\ /'''''''\ /'''''''''''''''\ /'''''''\ /''\ /''' DPE L / | | >------< x x x x >-< ,,,,,,,,,,,,,,,,,,,,,,,/| | | | \,,/ \,,,,,,,/ \,,,,,,,,,,,,,,,/ \,,,,,,,/ \,,/ | | | | | | | | | | | | | | -->| |<--Tdps | -->| |<---Tdps | | | | | | | | | | | | | | | | | -->| |<--Tdh | | -->| |<--Tdh | | | | | | | | | | | | | ''''''''''''''''''''''''''''''''''''''''''''''''''''\ /'''''''\ /'''''''''''''''\ /'''''''\ /'''''''''' CCTL L x | x x | x ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,/ | \,,,,,,,,,,,,,,,/ | \,,,,,,,,,, | | | | | | | | | | | | -->| |<--Tdalh -->| |<--Tdps | -->| |<--Tdps -->| | |<--Tsd | | | | | | | | | | | | | -->| | |<--Tdalhlz | -->| |<--Tdh | | -->| |<--Tdh | | | | | | | | | | | | | | | | '''''''''\ | /''''\ /''''''''''''\ | | /''\ /'''''''\ /'''''''''''''''\ /'''''''\ /''\ /''' CS/DP<3:0> >--------< x CS >------< x DP x x DP x >-< ,,,,,,,,,/ | \,,,,/ \,,,,,,,,,,,,/ | \,,/ \,,,,,,,/ \,,,,,,,,,,,,,,,/ \,,,,,,,/ \,,/ \,,, | | | | | | | | | CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 122 TIMING DIAGRAMS | | | | | | | | | | | -->| |<--Tasd | | | | -->| |<--Tasid | | | | | | | | | | AS L ''''''''''''''''''''''''''''''''''\ | | | | | | | /'''' | | \,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,/ | | | | | | | | | | | | | | | | | | | -->| |<--Tdsd | -->| |<--Tdsd | | | | | | | | | | | | | | | | -->| |<---Tdsid | -->| |<--Tdsid | | | | | | | | | | | DS L ''''''''''''''''''''''''''''''''''''''''''''''''\ | | | /''''''''''\ | | | /''''''''' | | | | \,,,,,,,,,,,,,,/ \,,,,,,,,,,,,,,/ | | | | | | | | | | | | | | | | | -->| |<--Tsd | | -->| |<--Tsid | | | | | | | | DBE L '''''''''''''''''''''''''''''''''''''''''\ | | | | /'''' | | | \,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,/ | | | | | | | | | | | | | -->| |<--Tsd -->| |<--Tbmh | | | | | | | | BM<3:0> L '''''''''''''''''''\ /'''''''\ /'''''''''''''''\ /''''''''''''''''''''''''''''''''''''''''''''''''''''' x x Valid BM x ,,,,,,,,,,,,,,,,,,,/ \,,,,,,,/ \,,,,,,,,,,,,,,,/ \,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, | | | | -->| |<--Tsd | | | | | | | | WR L ''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''' / \ | | ,,,,,,,,,,,,,,,,,,,,,,,/ \,,,,,, ->| |<--Tsws -->| |<--Tsws | | | | -->| | |<--Tswds -->| | |<--Tswds | | | | | | | | -->| |<--Tswh | | -->| |<--Tswh | | | | | | | | | | -->| | |<--Tswlmax | | -->| | |<--Tswlmax | | | | | | | | RDY L ''''''''''''''''''''''''''''''''''''''''''''''''''\ | | /'''''''''''\ | | /'''''''' ERR L \,,,,,,,,,,,,,/ \,,,,,,,,,,,,,/ CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 123 TIMING DIAGRAMS Ready slip timing: RDY L and ERR L are sampled internally coincident with data at T200 and T300. If either or both are asserted at T200 and T300, the microcycle finishes up as shown. If neither is asserted at sample point, the chip strobes (AS L, DS L, DBE L, etc.) remain unchanged and P1 following P4 are restarted. Thus the granularity at each sample point for RDY and ERR L slips is two clock cycles. Only a high to low (assertion) transition is allowed on RDYL and ERRL during a P4 that is part of a sample window. A low to high transition on RDYL and ERRL during this time will cause unpredictable results! Therefore, RDYL and ERRL must be negated (high) coming into a P4 that is part of a sample window if the intent is to have the CVAX CPU and CFPA see these signals negated. Interfacing note: RDYL and ERRL may be asserted coming into a P4 if they are to be asserted for the sample window; DAL<31:0> and CS/DP<3:0> L are three-stated on P2 of the address part of this cycle. CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 124 TIMING DIAGRAMS 7.10 CPU Write Cycle Internal phase P1 P3 P1 P3 P1 P3 P1 ____ ____ ____ ____ ____ ____ ____ CLKA 90% / \ /| \ /| \ /| \ /| \ / \ / \ / \ / | \ / | \ / | \ / | \ / \ / \ 10% / \____/ | \____/ | \____/ | \____/ | \____/ \____/ \____ | | | | | | | | Internal phase P2 | P4 | P2 | P4 | P2 P4 P2 ____ | ____ | ____ | ____ | ____ ____ ____ CLKB 90% \ / \ | /| \ | /| \ | / \ | /| \ / \ / \ / \ | / | \ | / | \ | / \ | / | \ / \ / 10% \____/ \____/ | \____/ | \____/ \____/ | \____/ \____/ | | | | | | | -->| ||<---Tdald | | | | | || | | | | | | || | -->| |<--Tdalh | -->| |<--Tdalh | || | | | | | | | | || | | | -->| |<--Tdald | | | || | | | | | | | | ''''''''''\ | /''''''''''''''''''''\ | /'''''''''''''''''''\ /'''''''''''''''\ /''''''\ /'''' DAL<31:00> >-------< address >----< write data x x >-----< ,,,,,,,,,,/ | \,,,,,,,,,,,,,,,,,,,,/ | \,,,,,,,,,,,,,,,,,,,/ \,,,,,,,,,,,,,,,/ \,,,,,,/ \,,,, | | | | | | | | | | | | | -->| |<--Tparityh | | | | | | | | -->| ||<--Tdald | -->| |<--Tparityd | | | || | | | | | | | ''''''''''''''''''''''''''''''''''''''''''''''''''\ | | | | /''''''''''''''''''''''''''''''''''''' DPE L / | | | \,,,,,,,,,,,,,,,,,/ ,,,,,,,,,,,,,,,,,,,,,,,/| | | | | | | | | -->| |<--Tdalh | -->| |<--Tparityh | | | | | | | | | -->| ||<--Tsd | | -->| |<--Tparityd | | | || | | | | | | | | '''''''''''''\ | /''''''''''''''''''''\ | /''''''''''''''''''\ /'''''''''''''''''''''''''\ /'''' CS/DP<3:0> >----< CS >----< DP x >-----< ,,,,,,,,,,,,,/ | \,,,,,,,,,,,,,,,,,,,,/ | \,,,,,,,,,,,,,,,,,,/ \,,,,,,,,,,,,,,,,,,,,,,,,,/ \,,,, | | | | | | | | | -->| |<--Tasd | | -->| |<--Tasid | | | | | | | | AS L ''''''''''''''''''''''''''''''''''\ | | | | | /'''''''''''''''''''''''''''''''''''''' | | \,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,/ | | | | | | | | | -->| |<---Tdsd | | | | | | | | | | | | | -->| |<--Tdsid | | | | | | | | DS L '''''''''''''''''''''''''''''''''''''''''''''''''\ | | /''''''''''''''''''''''''''''''''''''''''''''' | | | | \,,,,,,,,,,/ | | | | | | | CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 125 TIMING DIAGRAMS | | | | | | | | -->| |<--Tsd | | | | | | | | | | | | | | | -->| |<--Tsid | | | | | | | DBE L '''''''''''''''''''''''''''''''''''''''''\ | | | /'''''''''''''''''''''''''''''''''''''' | | | \,,,,,,,,,,,,,,,,,,,,,,,,,/ | | | | | | | | | | | -->| |<--Tsd -->| |<--tbmh | | | | | | BM<3:0> L '''''''''''''''''''''''''''''\ /''''''''''''''''\ /''''''''''''''''''''''''''''''''''''''''''''''''''''''''' x valid BM x (see note below) ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,/ \,,,,,,,,,,,,,,,,/ \,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, | | | -->| |<--Tsd -->| |<--Tbmh | | | | WR L ''''''''''''''''''''''\ | /''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''' \ | / ,,,,,,,,,,,,,,,,,,,,,,,,\,,,,,,,,,,,,,/,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, | -->| |<--Tsws | | -->| | |<--Tswds | | | | | -->| |<--Tswh | | | | | | -->| | |<--Tswlmax | | | | RDY L ''''''''''''''''''''''''''''''''''''''''''''''''''\ | | /''''''''''''''''''''''''''''''''''''''''' ERR L \,,,,,,,,,,,,,/ CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 126 TIMING DIAGRAMS Ready slip timing: RDY L and ERR L are sampled internally at T200. If either or both are asserted, the microcycle finishes up as shown. If neither is asserted, the chip strobes (AS L, DS L, DE L, etc.) remain unchanged and P1 following P4 are restarted. Thus the granularity for RDY and ERR L slips is two clock cycles. Only a high to low (assertion) transition is allowed on RDYL and ERRL during a P4 that is part of a sample window. A low to high transition on RDYL and ERRL during this time will cause unpredictable results! Therefore, RDYL and ERRL must be negated (high) coming into a P4 that is part of a sample window if the intent is to have the CVAX CPU and CFPA see these signals negated. Interfacing note: RDYL and ERRL may be asserted coming into a P4 if they are to be asserted for the sample window; DAL<31:0> and CS/DP<3:0> L are three-stated on P2 of the address part of this cycle; although not tested, byte mask will also be valid after the write data is stable on DAL<31:0>. CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 127 TIMING DIAGRAMS 7.11 CFPA Interface Timing 7.11.1 Opcode Transfers - Internal phase P1 P3 P1 P3 ____ ____ ____ ____ CLKA 90% / \ /| \ / \ / \ / \ / | \ / \ / \ 10% / \____/ | \____/ \____/ \____ | | Internal phase P2 | P4 P2 P4 ____ | ____ ____ ____ CLKB 90% \ / \ | / \ /| \ / \ / \ | / \ / | \ / 10% \____/ \____/ \____/ | \____/ | | -->| |<--Tcpd -->| |<--Tcpdh | | | | _____________ ____________________ _______ \ / F/D, G or Integer \ / CPSTA<1:0> H >----< opcode on CDDAT >----< _____________/ \____________________/ \_______ | | | | -->| |<--Tcpd -->| |<--Tcpdh | | | | _____________ ____________________ _______ \ / \ / CPDAT<5:0> H >----< Opcode <5:0> >----< _____________/ \____________________/ \_______ |<--- execution of new ---->| | VAX instruction | | begins | This timing is used when CVAX CPU signals Opcode on CPDAT. Interfacing note: CPDAT and CPSTA are three-stated on P2. CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 128 TIMING DIAGRAMS 7.11.2 Single Precision CVAX CPU To CFPA Transfer - Internal phase P1 P3 P1 P3 ____ ____ ____ ____ CLKA 90% / \ /| \ / \ / \ / \ / | \ / \ / \ 10% / \____/ | \____/ \____/ \____ | | Internal phase P2 | P4 P2 P4 ____ | ____ ____ ____ CLKB 90% \ / \ | / \ /| \ / \ / \ | / \ / | \ / 10% \____/ \____/ \____/ | \____/ | | -->| |<--Tcpd -->| |<--Tcpdh | | | | _____________ | | | | _______ \ | | | | / CPSTA<1:0> H >----< | | | >---< _____________/ | \_____________________/ \_______ | | | | -->| |<--Tcpd -->| |<--Tcpdh | | | | _____________ | ____________________ _______ \ | / operand on \ / CPDAT<5:0> H >----< DAL >----< _____________/ | \____________________/ \_______ | | | -->| |<--Tdalh | | | -->| |<--Tdald | | | | | '''''''''''''\ /''''''''''''''''''''\ /''''''' DAL<31:00> >----< operand >----< ,,,,,,,,,,,,,/ \,,,,,,,,,,,,,,,,,,,,/ \,,,,,,, AS L ''''''''''''''/''''''''''''''''''''''''''''''''''''''''' ,,,,,,,,,,,,,/ This timing is used when CVAX CPU signals OPERAND ON DAL and AS L is not asserted. When AS L is asserted, the CFPA reads the operand information off of the DAL according to the full memory read protocol. Interfacing note: DAL, CPDAT and CPSTA are three-stated on P2. CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 129 TIMING DIAGRAMS 7.11.3 Double Precision CVAX CPU To CFPA Transfer - Internal phase P1 P3 P1 P3 P1 P3 ____ ____ ____ ____ ____ ____ CLKA 90% / \ /| \ / \ /| \ / \ /| \ / / \ / | \ / \ / | \ / \ / \ / 10% / \____/ | \____/ \____/ | \____/ \____/ \____/ | | | | Internal phase P2 | P4 P2 | P4 P2 P4 ____ | ____ ____ | ____ ____ ____ CLKB 90% \ / \ | / \ /| \ | / \ /| \ / \ \ / \ | / \ / | \ | / \ / | \ / \ 10% \____/ \____/ \____/ | \____/ \____/ | \____/ \ | | | | -->| |<--Tcpd | -->| |<--Tcpd | | | | | | | | | -->| |<--Tcpdh | -->| |<--Tcpdh | | | | | | | | _____________ | | | | | | | | _________ \ | | | | | | | | / CPSTA<1:0> H >----< | | | >----< | | | >----< _____________/ | \____________________/ | \____________________/ \_________ | | | | | | | | -->| |<--Tcpd | -->| |<--Tcpd | | | | | | | | | -->| |<--Tcpdh | -->| |<--Tcpdh | | | | | | | | _____________ | ____________________ | ____________________ _________ \ | / 1st operand on \ | / 2nd operand on \ / CPDAT<5:0> H >----< DAL >----< DAL >----< _____________/ | \____________________/ | \____________________/ \_________ | | | | | | | | | -->| |<--Tdalh -->| |<--Tdalh | | | | -->| |<--Tdald | -->| |<--Tdald | | | | | '''''''''''''\ /''''''''''''''''''''\ /''''''''''''''''''''\ /''''''''' DAL<31:00> >----< first operand >----< second operand >----< ,,,,,,,,,,,,,/ \,,,,,,,,,,,,,,,,,,,,/ \,,,,,,,,,,,,,,,,,,,,/ \,,,,,,,,, AS L ''''''''''''''/''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''' ,,,,,,,,,,,,,/ This timing is used when CVAX CPU signals OPERAND ON DAL and AS L is not asserted. When AS L is asserted, the CFPA reads the operand information off of the DAL according to the full memory read protocol. AS L may be asserted for either the first or second operand, or both operands. Interfacing note: DAL, CPDAT and CPSTA are three-stated on P2. CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 130 TIMING DIAGRAMS 7.11.4 Single Precision CFPA To CVAX CPU Transfers - Internal phase P3 P1 P3 P1 P3 P1 P3 P1 ___ ___ ___ ___ ___ ___ ___ ___ CLKA 90% /| \ / \ / \ /| \ / \ /| \ /| \ / \ / | \ / \ / ... / | \ / \ / | \ / | \ / \ 10% / | \___/ \___/ \___/ | \___/ \___/ | \___/ | \___/ \___/ | | | | | | | | Internal phase | P4 P2 P4 | P2 P4 | P2 | P4 P2 | ___ ___ ___ | ___ ___ | ___ | ___ ___ CLKB 90% \ | / \ /| \ / \ | / \ / \ | / \ | / \ / \ \ | / \ / | \ ... \ | / \ / \ | / \ | / \ / 10% \___/ \___/ | \___/ \___/ \___/ \___/ \___/ \___/ | | | | | | -->| |<--Tcpdh | | | | | | -->| |<--Tcps -->| |<--Tcps | | | | | | | | | -->| |<--Tcpd | | |-->| |<--Tcph |-->| |<---Tcph | | | | | | | | | | | | | -->| | |<---Tcphlz | | | | | -->| |<--Tcpd | | | | | | | | | | | | | ______ | | | | _________ _________ _________ _ | __________________ \ | | | | / CCs \ / \ / result \ / \ | / CPSTA<1:0> H x | | | x------< ready x x ready x >---< ______/ \________________/ \_________/ \_________/ \_________/ \_/ | \__________________ | | | | | | | | | | | -->| |<--Tcpdh | | | | | | -->| |<--Tcps -->| |<--Tcps | -->| |<--Tcpd | | | | | | | | | | |-->| |<--Tcph |-->| |<---Tcph | | | | | | | | | | -->| | |<---Tcphlz | | | | -->| |<--Tcpd | | | | | | | | | | ______ _______________ | _________ _________ _________ _ | ____________________ \ / ready for \ | / no \ / \ / \ / \ | / CPDAT<5:0> H x result >-------< error x x last x >---< ______/ \_______________/ \_________/ \_________/ \_________/ \_/ | \____________________ | | -->| |<--Tds | | | | | | -->| |<--Tdald | | | | -->| |<--Tdh | | | | ''''''''''''''''''''''''\ /'''\ /'''''''''\ /''\ /'''''''''''''''' DAL<31:00> >-------------------------< x result x >------< ,,,,,,,,,,,,,,,,,,,,,,,,/ \,,,/ \,,,,,,,,,/ \,,/ \,,,,,,,,,,,,,,,, ''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''' DMG L ,,,,,,,,,,,,,,,,,,,,,,,,,,,/ --------------------->| |<--------------------->|<----------------------->| |<--------------- CVAX DAL, CPDAT, and | | CFPA CPDAT | CFPA DAL, CPDAT | | CVAX DAL, CPDAT CPSTA master | | and CPSTA master | and CPSTA master | | and CPSTA master CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 131 TIMING DIAGRAMS The CFPA starts to drive CPDAT and CPSTA lines on a P3 edge after receiving a READY FOR RESULT command from CVAX CPU. The CFPA starts to drive DAL lines on the P3 edge after sending NO FATAL ERROR and CONDITION CODES READY status back to CVAX CPU. while DMG L is not asserted. The CFPA three-states DAL, CPDAT, and CPSTA on the P2 edge after either sending back a FATAL ERROR status or the last longword result. CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 132 TIMING DIAGRAMS 7.11.5 Double Precision CFPA To CVAX CPU Transfers - Internal phase P3 P1 P3 P1 P3 P1 P3 P1 P3 ___ ___ ___ ___ ___ ___ ___ ___ ___ CLKA 90% /| \ / \ / \ /| \ / \ /| \ / \ /| \ /| \ / | \ / \ / ... / | \ / \ / | \ / \ / | \ / | \ 10% / | \___/ \___/ \___/ | \___/ \___/ | \___/ \___/ | \___/ | \___ | | | | | | | | | | Internal phase | P4 P2 P4 | P2 P4 | P2 P4 | P2 | P4 | ___ ___ ___ | ___ ___ | ___ ___ | ___ | ___ CLKB 90% \ | / \ /| \ / \ | / \ / \ | / \ / \ | / \ | / \ | / \ / | \ ... \ | / \ / \ | / \ / \ | / \ | / 10% \___/ \___/ | \___/ \___/ \___/ \___/ \___/ \___/ \___/ | | | | | | | -->| |<--Tcpdh | | | | | | | -->| |<--Tcps -->| |<--Tcps -->| |<--Tcps | | | | | | | | | | | -->| |<--Tcpd | | |-->| |<--Tcph |-->| |<--Tcph |-->| |<---Tcph | | | | | | | | | | | | | | | | -->| | |<---Tcphlz | | | | | | | | -->| | H x | | | x------< ready x x ready x x ready x >---< ______/ \________________/ \_________/ \_________/ \_________/ \_________/ \_________/ \_/ | \_____ | | | | | | | -->| |<--Tcpdh | | | | | | | -->| |<--Tcps -->| |<--Tcps -->| |<--Tcps | -->| |<--Tcpd | | | | | | | | | | | | |-->| |<--Tcph |-->| |<--Tcph |-->| |<---Tcph | | | | | | | | | | | | | -->| | |<---Tcphlz | | | | | | | -->| | H x result >-------< error x x last x x last x >---< ______/ \_______________/ \_________/ \_________/ \_________/ \_________/ \_________/ \_/ | \_____ | | | -->| |<--Tds -->| |<--Tds | | | | | | | | | | Tdald -->| |< | | | | | | -->| |<--Tdh | -->| |<---Tdh | | | | | | ''''''''''''''''''''''''\ /'''\ /'''''''''\ /'''''''''\ /'''''''''\ /''\ /' DAL<31:00> >-------------------------< x result 1 x x result 2 x >------< ,,,,,,,,,,,,,,,,,,,,,,,,/ \,,,/ \,,,,,,,,,/ \,,,,,,,,,/ \,,,,,,,,,/ \,,/ \, '''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''' DMG L ,,,,,,,,,,,,,,,,,,,,,,,,,,,/ --------------------->| |<--------------------->|<---------------------------------------->| |<------- CVAX DAL, CPDAT, and | | CFPA CPDAT | CFPA DAL, CPDAT, and | | CVAX DA CPSTA master | | and CPSTA master | CPSTA master | | and CPS CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 133 TIMING DIAGRAMS The CFPA starts to drive CPDAT and CPSTA lines on a P3 edge after receiving a READY FOR RESULT command from CVAX. The CFPA starts to drive DAL lines on the P3 edge after sending NO FATAL ERROR and CONDITION CODES READY status back to CVAX. while DMG L is not asserted. The CFPA three-states DAL, CPDAT, and CPSTA on the P2 edge after either sending back a FATAL ERROR status or the last longword. CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 134 CHIP INTERCONNECT DIAGRAM 8 CHIP INTERCONNECT DIAGRAM CLKA---------+ | CLKB-------+ | | | VCC -----+ | | +----- GND | | | | V V V V +-------+ IRQ<3:0> L ------------------->| |<---------------------+-----------------------------> AS L | | | | | | +-------+ INTTIM L ------------------->| | |------->| | | | DAL<31:00> | | | | |<--------------+-------------->| latch |------------> BA<29:00> | | | | | | | | | | +-------+ | | | | PWRFL L ------------------->| | | | +-------+ | | | | |trans- | | | +-------------->|ceiver |<-----------> BD<31:00> CRD L ------------------->| | | | | | CVAX | | +-------+ | CPU | | ^ ^ CWB L <-------------------| Chip | | | | | |---------------------------------+---|--------------> DBE L | | | | | MEMERR L ------------------->| | | | | | |-------------------------------------+--------------> WR L | | | | | HALT L ------------------->| | | | | | |----------------------------------------------------> DS L | | | | | ERR L ------------------->| | | | | | | | v v | | | +-------+ RDY L ------------------->| | CS/DP<3:0> L | |trans- | | |<--------------+-------------->|eiver |<-----------> Parity | | | | | | CCTL L ------------------->| | | | +-------+ | | | | | | | | +-------+ RESET L ------------------->| | | +------->| | | | | | latch | | | +-------------->| |<-----------> Cycle status DMR L ------------------->| | +-------+ | | | | DMG L <-------------------| |----------------------------------------------------> BM <3:0> L | | | | TEST H/Vss ------------------>| |<----------------------------------------------------> coprocessor functions +-------+ CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 135 DIFFERENCES BETWEEN CVAX DC341/DC580 AND MICROVAX DC333 9 DIFFERENCES BETWEEN CVAX DC341/DC580 AND MICROVAX DC333 9.1 SOFTWARE DIFFERENCES The following list highlights the specific software differences that exist between the MicroVAX (uVAX) DC333 and the two CVAX CPUs: As the CVAX CPUs are identical in function they shall be referred to as CVAX. uVAX CVAX ---- ---- X 1. IPR 37 is defined as the CADR, and IPR 39 is defined as the MSER. MFPR/MTPR access these registers X IPR 37 and IPR 39 are not defined. MFPR/MTPR can not access these register unless they are externally defined. X 2. IPR 41 is defined as an accelerator (coprocessor) maintenance register. X IPR 41 is defined as the console saved interrupt stack pointer. X 3. Processor registers 7:5, 15:14, 23:24, 41:40, and 47:44 are external registers. X Processor registers 7:5, 15:14, 23:24, 40, and 47:44 are reserved registers; 41 is defined as the console saved interrupt stack pointer. X 4. Index immediate mode causes a reserve addressing error. X Index immediate mode does not cause a reserve addressing error. X 5. The saved PSL and PC are not initialized at power up. Therefore, the SAVPSL valid flag is unpredictable. X At power up (RESET L asserted), the saved PSL and PC are initialized to 041F0000 and 2004000 (hex), respectively. The SAVPSL flag is always 0. X 6. The following character string instructions are executed: CMPC3, CMPC5, LOCC, SCANC, SKPC, and SPANC. CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 136 DIFFERENCES BETWEEN CVAX DC341/DC580 AND MICROVAX DC333 X The following character string instructions are emulated: CMPC3, CMPC5, LOCC, SCANC, SKPC, and SPANC. X 7. POLYf (with CFPA) is not suspendable. X POLYf (with F-chip) is suspendable . 9.2 HARDWARE DIFFERENCES The intent of this section is provide an overview of the major hardware differences between the CVAX CPU and the MicroVAX CPU. In general, CVAX is targeted as a functional replacement for MicroVAX, and not as a pin for pin replacement. Although the basic sequencing and functionality of the strobe signals (AS L, DS L, and DBE L) is the same for both uVAX and CVAX, the AC timing is quite different. Refer to the AC Characteristics in each CPU specification for the specific timing. In addition, the coprocessor protocol is very different. Refer to the coprocessor protocol descriptions in each CPU specification for details. A MicroVAX coprocessor can not be used with CVAX. The following list highlights the specific hardware differences that exist between the two CPUs: uVAX CVAX ---- ---- X 1. The minimum I/O cycle length is four clock phases. X The minimum I/O cycle length is eight clock phased. X 2. The minimum I/O cycle slip is two clock phases. X The minimum I/O cycle slip is four clock phases. X 3. RDY L and ERR L are externally synchronized. The ready and/or error signals can be asserted with the read data. Error reporting during a minimum I/O cycle is possible. X RDY L and ERR L are internally synchronized. The ready or error signals must be asserted before the read data. Error reporting during a minimum I/O cycle is not possible. X 4. An I/O cycle retry is requested when both CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 137 DIFFERENCES BETWEEN CVAX DC341/DC580 AND MICROVAX DC333 RDY L and ERR L are asserted. X Processor does not support I/O cycle retries. X 5. External processor protocol uses a normal I/O cycle. RDY L or ERR L must be asserted to terminate the cycle. X External processor protocol uses a EPS cycle. RDY L or ERR L are not asserted to terminate the cycle. X 6. Parity protection is provided for DAL read and write data. DPE L allows external logic to select whether they support parity. A Memory System Error Register (MSER) is implemented which logs parity errors. X No parity protection is provided. X 7. Cycle status lines are time-multiplexed with parity information. This may require an external cycle status latch. X Cycle status lines are driven on dedicated pins. No external cycle status latch is needed. X 8. Interrupt acknowledge cycles drive the interrupt grant level on DAL<6:2>. X Interrupt acknowledge cycles drive the interrupt grant level on DAL<4:0>. X 9. Cacheable reads generate a multiple transfer cycle to read two longwords. X Only single transfer read cycles are supported. X 10. The CPU contains a 1Kb cache. Data caching can be prevented by asserting CCTL L, and DMA cache invalidates can be requested by asserting CCTL L. A cache disable register (CADR) is implemented. X The CPU does not contain a cache. X 11. A clear write buffer signal (CWB L) is provided that informs external logic when an REI instruction is executed. X No clear write buffer signal is provided. CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 138 DIFFERENCES BETWEEN CVAX DC341/DC580 AND MICROVAX DC333 X 12. Operand read references for MOVC3/MOVC5 appear as demand D-stream reads. X Operand read references for MOVC3/MOVC5 appear as I-stream reads. X 13. HALT L interrupt is not acknowledged. X HALT L interrupt is acknowledged by a EPS write to register 64. X 14. IPR number driven out on DAL<7:2> during external processor cycles. X IPR number driven out on DAL<5:0> during EPS cycles. X 15. DAL<31:30> is driven with 01 for single longword transfers and 10 for quadword multiple transfers when an address is driven on DAL<29:0> (DAL<31:30> = 11 is reserved for DMA octaword transfers; 00, DMA hexword transfers). X DAL<31:30> is driven with 00 for byte, 01 for word, 10 for longword and 11 for quadword when an address is driven on DAL<29:0>. CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 139 PACKAGE PINOUT 10 PACKAGE PINOUT |<-CPSTA->||<-----------CPDAT---------->| DAL DAL DAL DAL DAL DAL DAL IRQ<0> <0> <1> <0> <1> <2> <3> <4> <5> Vss Vdd <31> <30> <29> <28> <27> <26> <25> Vdd Vdd Vss | | | | | | | | | | | | | | | | | | | | | .--+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+---+---+--. | 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 | IRQ<1>--+ 12 74 +--DAL<24> | | IRQ<2>--+ 13 73 +--DAL<23> | | IRQ<3>--+ 14 72 +--DAL<22> | | INTTIM--+ 15 71 +--DAL<21> | CVAX Package Pinout | CRD--+ 16 70 +--DAL<20> | | MEMERR--+ 17 69 +--DAL<19> | | PWRFL--+ 18 68 +--DAL<18> | | HALT--+ 19 67 +--DAL<17> | | EST/Vss--+ 20 66 +--DAL<16> | | Vdd--+ 21 65 +--DAL<15> | | Vss--+ 22 64 +--DAL<14> | | CWB--+ 23 63 +--DAL<13> | | CCTL--+ 24 62 +--DAL<12> | | DMG--+ 25 61 +--DAL<11> | | DMR--+ 26 60 +--DAL<10> | | RDY--+ 27 59 +--DAL<9> | | ERR--+ 28 58 +--DAL<8> | | DS--+ 29 57 +--DAL<7> | | AS--+ 30 56 +--DAL<6> | | DBE--+ 31 55 +--DAL<5> | | WR--+ 32 54 +--DAL<4> | 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 | `--+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+---+---+--' | | | | | | | | | | | | | | | | | | | | | CLKB CLKA | Vdd Vss DPE CSDP CSDP CSDP CSDP BM BM BM BM DAL DAL DAL DAL Vss Vss Vdd RESET <3> <2> <1> <0> <3> <2> <1> <0> <0> <1> <2> <3> CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 140 BONDING PINOUT 11 BONDING PINOUT DAL DAL DAL DAL DAL DAL DAL |<---------CPDAT------------>||<-CPSTA->| Vss Vdd Vdd <25> <26> <27> <28> <29> <30> <31> Vdd Vss <5> <4> <3> <2> <1> <0> <1> <0> IRQ<0> | | | | | | | | | | | | | | | | | | | | | .--+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+---+---+--. | 75 76 77 78 79 80 81 82 83 84 1 2 3 4 5 6 7 8 9 10 11 | DAL<24>--+ 74 12 +--IRQ<1> | | DAL<23>--+ 73 13 +--IRQ<2> | | DAL<22>--+ 72 14 +--IRQ<3> | | DAL<21>--+ 71 15 +--INTTIM | CVAX Bonding Pinout | DAL<20>--+ 70 16 +--CRD | | DAL<19>--+ 69 17 +--MEMERR | | DAL<18>--+ 68 18 +--PWRFL | | DAL<17>--+ 67 19 +--HALT | | DAL<16>--+ 66 20 +--TEST/Vss | | DAL<15>--+ 65 21 +--Vdd | | DAL<14>--+ 64 22 +--Vss | | DAL<13>--+ 63 23 +--CWB | | DAL<12>--+ 62 24 +--CCTL | | DAL<11>--+ 61 25 +--DMG | | DAL<10>--+ 60 26 +--DMR | | DAL<9>--+ 59 27 +--RDY | | DAL<8>--+ 58 28 +--ERR | | DAL<7>--+ 57 29 +--DS | | DAL<6>--+ 56 30 +--AS | | DAL<5>--+ 55 31 +--DBE | | DAL<4>--+ 54 32 +--WR | 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 | `--+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+---+---+--' | | | | | | | | | | | | | | | | | | | | | Vdd Vss Vss DAL DAL DAL DAL BM BM BM BM CSDP CSDP CSDP CSDP DPE Vss Vdd | CLKA CLKB <3> <2> <1> <0> <0> <1> <2> <3> <0> <1> <2> <3> RESET CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 141 CVAX INSTRUCTION TIMING 12 CVAX INSTRUCTION TIMING The execution time of an instruction depends on the instruction itself, the addressing modes of the instruction specifiers, and the special cases invoked by the instruction (cache miss, TB miss, unaligned operand, etc). In the most general case, the instruction execution time is the sum of the specifier times and the execute, fetch time. inst time = spec 1 time +...+ spec n time + execute, fetch time All times are given in microcycles and I/O cycles. A number 'n' represents n microcycles; 'n'R represents n read cycles; and 'n'W represents n write cycles. Read cycles that hit in the cache take 1 microcycle; read cycles that miss in the cache take at least 1 extra cycle, depending on the speed of external memory. Write cycles always take one cycle, unless the external interface is busy. CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 142 CVAX INSTRUCTION TIMING 12.1 Specifier Timing The first table covers all specifiers except the last; the second and third tables cover the last specifier. Specifier addressing modes are cross-indexed with specifier access type: r = read a = address v = field m = modify w = write and data length: b = byte w = word l = long or f_floating q = quadword or d_floating or g_floating. Branch displacements are NOT considered to be specifiers; handling of branch displacements is included in the execute, fetch timing tables. 12.1.1 Specifier Timing (Not The Last Specifier) - Only access types a, v, and r occur in these specifiers. addressing mode | r.bwl av.bwl r.q av.q ---------------------------+-------------------------------- not indexed: | short literal #n | 1 - 2 - register Rn | 1 1 2 2 register def (Rn) | 1+1r 1 1+2r 1 autodecrement -(Rn) | 2+1r 2 2+2r 2 autoincrement (Rn)+ | 2+1r 2 2+2r 2 immediate i^#n | 2 2 4 4 autoinc def @(Rn)+ | 2+2r 2+1r 2+3r 2+1r absolute @#a | 1+1r 1 1+2r 1 displ/relative d(Rn) | 1+1r 1 1+2r 1 displ/rel def @d(Rn) | 1+2r 1+1r 1+3r 1+1r indexed: | short literal | - - - - register | - - - - register def (Rn)[Rx] | 2+1r 2 2+2r 2 autodecrement -(Rn)[Rx] | 3+1r 3 3+2r 3 autoincrement (Rn)+[Rx] | 3+1r 3 3+2r 3 immediate | - - - - autoinc def @(Rn)+[Rx] | 4+2r 4+1r 4+2r 4+1r absolute @#a[Rx] | 2+1r 2 2+2r 2 displ/relative d(Rn)[Rx] | 3+1r 3 3+2r 3 displ/rel def @d(Rn)[Rx] | 3+2r 3+1r 3+3r 3+1r CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 143 CVAX INSTRUCTION TIMING 12.1.2 Specifier Timing (Last Specifier) - Access types a, v, r, m, and w are permitted in the last specifier. This table covers data lengths byte, word, and long. addressing mode | r.bwl av.bwl m.bwl w.bwl ---------------------------+-------------------------------- not indexed: | short literal #n | 1 - - - register Rn | 0 0 0 1 register def (Rn) | 1+1r 1 1+1r+1w 1+1w autodecrement -(Rn) | 2+1r 2 2+1r+1w 2+1w autoincrement (Rn)+ | 2+1r 2 2+1r+1w 2+1w immediate i^#n | 2 2 - - autoinc def @(Rn)+ | 2+2r 2+1r 2+2r+1w 2+1r+1w absolute @#a | 1+1r 1 1+1r+1w 1+1w displ/relative d(Rn) | 1+1r 1 1+1r+1w 1+1w displ/rel def @d(Rn) | 1+2r 1+1r 1+2r+1w 1+1r+1w indexed: | short literal | - - - - register | - - - - register def (Rn)[Rx] | 2+1r 2 2+1r+1w 2+1w autodecrement -(Rn)[Rx] | 3+1r 3 3+1r+1w 3+1w autoincrement (Rn)+[Rx] | 3+1r 3 3+1r+1w 3+1w immediate | - - - - autoinc def @(Rn)+[Rx] | 4+2r 4+1r 4+2r+1w 4+1r+1w absolute @#a[Rx] | 2+1r 2 2+1r+1w 2+1w displ/relative d(Rn)[Rx] | 3+1r 3 3+1r+1w 3+1w displ/rel def @d(Rn)[Rx] | 3+2r 3+1r 3+2r+1w 3+1r+1w This table covers data length quad. Note that back to back writes stall for one cycle; this is already included in the modify and write columns. CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 144 CVAX INSTRUCTION TIMING addressing mode | r.q av.q m.q w.q ---------------------------+-------------------------------- not indexed: | short literal #n | 2 - - - register Rn | 0 0 2 2 register def (Rn) | 1+2r 1 2+2r+2w 2+2w autodecrement -(Rn) | 2+2r 2 3+2r+2w 3+2w autoincrement (Rn)+ | 2+2r 2 3+2r+2w 3+2w immediate i^#n | 4 4 - - autoinc def @(Rn)+ | 2+3r 2+1r 3+3r+2w 3+1r+2w absolute @#a | 1+2r 1 2+2r+2w 2+2w displ/relative d(Rn) | 1+2r 1 2+2r+2w 2+2w displ/rel def @d(Rn) | 1+3r 1+1r 2+3r+2w 2+1r+2w indexed: | short literal | - - - - register | - - - - register def (Rn)[Rx] | 2+2r 2 3+2r+2w 3+2w autodecrement -(Rn)[Rx] | 3+2r 3 4+2r+2w 4+2w autoincrement (Rn)+[Rx] | 3+2r 3 4+2r+2w 4+2w immediate | - - - - autoinc def @(Rn)+[Rx] | 4+3r 4+1r 5+3r+2w 5+1r+2w absolute @#a[Rx] | 2+2r 2 3+2r+2w 3+2w displ/relative d(Rn)[Rx] | 3+2r 3 4+2r+2w 4+2w displ/rel def @d(Rn)[Rx] | 3+3r 3+1r 4+3r+2w 4+1r+2w CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 145 CVAX INSTRUCTION TIMING 12.2 Execute, Fetch Timing The execute, fetch timing covers the execution time of the current instruction and the normally buried prefetch time for the next instruction. If the current instruction is a branch, the fetch time of the next instruction cannot be buried and is accounted for in this table. The standard notation for operand specifiers is: . where: 1. Name is a suggestive name for the operand in the context of the instruction. It is the capitalized name of a register or block for implied operands. 2. Access type is a letter denoting the operand specifier access type. a = address operand b = branch displacement m = modified operand (both read and written) r = read only operand v = field operand w = write only operand 3. Data type is a letter denoting the data type of the operand. b = byte d = d_floating f = f_floating g = g_floating l = longword q = quadword v = field (used only in implied operands) w = word * = multiple longwords (used only in implied operands) 4. Implied operands, that is, locations that are accessed by the instruction, but not specified in an operand, are denoted by curly braces {}. 12.2.1 Integer Arithmetic And Logical Instructions - Opcode Instruction Execution Cycles ------ ----------- ---------------- 58 ADAWI add.rw, sum.mw 1 sum = reg 4 sum = mem CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 146 CVAX INSTRUCTION TIMING 80 ADDB2 add.rb, sum.mb 1 C0 ADDL2 add.rl, sum.ml 1 A0 ADDW2 add.rw, sum.mw 1 81 ADDB3 add1.rb, add2.rb, sum.wb 1 C1 ADDL3 add1.rl, add2.rl, sum.wl 1 A1 ADDW3 add1.rw, add2.rw, sum.ww 1 D8 ADWC add.rl, sum.ml 1 78 ASHL cnt.rb, src.rl, dst.wl 5-8, 7 typ 79 ASHQ cnt.rb, src.rq, dst.wq 4-8, 7 typ 8A BICB2 mask.rb, dst.mb 1 CA BICL2 mask.rl, dst.ml 1 AA BICW2 mask.rw, dst.mw 1 8B BICB3 mask.rb, src.rb, dst.wb 1 CB BICL3 mask.rl, src.rl, dst.wl 1 AB BICW3 mask.rw, src.rw, dst.ww 1 88 BISB2 mask.rb, dst.mb 1 C8 BISL2 mask.rl, dst.ml 1 A8 BISW2 mask.rw, dst.mw 1 89 BISB3 mask.rb, src.rb, dst.wb 1 C9 BISL3 mask.rl, src.rl, dst.wl 1 A9 BISW3 mask.rw, src.rw, dst.ww 1 93 BITB mask.rb, src.rb 1 D3 BITL mask.rl, src.rl 1 B3 BITW mask.rw, src.rw 1 94 CLRB dst.wb 2 dst = reg 1 dst = mem D4 CLRL{=F} dst.wl 2 dst = reg 1 dst = mem 7C CLRQ{=D=G} dst.wq 3 dst = reg 1 dst = mem B4 CLRW dst.ww 2 dst = reg 1 dst = mem 91 CMPB src1.rb, src2.rb 1 D1 CMPL src1.rl, src2.rl 1 B1 CMPW src1.rw, src2.rw 1 98 CVTBL src.rb, dst.wl 2 99 CVTBW src.rb, dst.wl 2 F6 CVTLB src.rl, dst.wb 4-5, 4 typ F7 CVTLW src.rl, dst.ww 4-5, 4 typ 33 CVTWB src.rw, dst.wb 4-5, 4 typ 32 CVTWL src.rw, dst.wl 2 CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 147 CVAX INSTRUCTION TIMING 97 DECB dif.mb 3 dst = reg 1 dst = mem D7 DECL dif.ml 3 dst = reg 1 dst = mem B7 DECW dif.mw 3 dst = reg 1 dst = mem 86 DIVB2 divr.rb, quo.mb 16-19, 17 typ C6 DIVL2 divr.rl, quo.ml 39-43, 40 typ w/o FPA tbd with FPA A6 DIVW2 divr.rw, quo.mw 24-27, 25 typ 87 DIVB3 divr.rb, divd.rb, quo.wb 16-19, 17 typ C7 DIVL3 divr.rl, divd.rl, quo.wl 39-43, 40 typ w/o FPA tbd with FPA A7 DIVW3 divr.rw, divd.rw, quo.ww 24-27, 25 typ 7B EDIV divr.rl, divd.rq, quo.vl, rem.wl 47-52, 48 typ 7A EMUL mulr.rl, muld.rl, add.rl, prod.wq 36 w/o FPA tbd with FPA 96 INCB sum.mb 3 dst = reg 1 dst = mem D6 INCL sum.ml 3 dst = reg 1 dst = mem B6 INCW sum.mw 3 dst = reg 1 dst = mem 92 MCOMB src.rb, dst.wb 0 dst = reg 1 dst = mem D2 MCOML src.rl, dst.wl 0 dst = reg 1 dst = mem B2 MCOMW src.rw, dst.ww 0 dst = reg 1 dst = mem 8E MNEGB src.rb, dst.wb 0 dst = reg 1 dst = mem CE MNEGL src.rl, dst.wl 0 dst = reg 1 dst = mem AE MNEGW src.rw, dst.ww 0 dst = reg 1 dst = mem 90 MOVB src.rb, dst.wb 0 D0 MOVL src.rl, dst.wl 0 7D MOVQ src.rq, dst.wq 0 B0 MOVW src.rw, dst.ww 0 9A MOVZBW src.rb, dst.wb 0 9B MOVZBL src.rb, dst.wl 0 3C MOVZWL src.rw, dst.ww 0 84 MULB2 mulr.rb, prod.mb 14 C4 MULL2 mulr.rl, prod.ml 37 w/o FPA CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 148 CVAX INSTRUCTION TIMING tbd with FPA A4 MULW2 mulr.rw, prod.mw 21 85 MULB3 mulr.rb, muld.rb, prod.wb 14 C5 MULL3 mulr.rl, muld.rl, prod.wl 37 w/o FPA tbd with FPA A5 MULW3 mulr.rw, muld.rw, prod.ww 21 DD PUSHL src.rl, {-(SP).wl} 2+1w 9C ROTL cnt.rb, src.rl, dst.wl 3 D9 SBWC sub.rl, dif.ml 1 82 SUBB2 sub.rb, dif.mb 1 C2 SUBL2 sub.rl, dif.ml 1 A2 SUBW2 sub.rw, dif.mw 1 83 SUBB3 sub.rb, min.rb, dif.wb 1 C3 SUBL3 sub.rl, min.rl, dif.wl 1 A3 SUBW3 sub.rw, min.rw, dif.ww 1 95 TSTB src.rb 2 src = reg 1 src = mem D5 TSTL src.rl 2 src = reg 1 src = mem B5 TSTW src.rw 2 src = reg 1 src = mem 8C XORB2 mask.rb, dst.mb 1 CC XORL2 mask.rl, dst.ml 1 AC XORW2 mask.rw, dst.mw 1 8D XORB3 mask.rb, src.rb, dst.wb 1 CD XORL3 mask.rl, src.rl, dst.wl 1 AD XORW3 mask.rw, src.rw, dst.ww 1 12.2.2 Address Instructions - Opcode Instruction Execution Cycles ------ ----------- ---------------- 9E MOVAB src.ab, dst.wl 0 DE MOVAL{=F} src.al, dst.wl 0 7E MOVAQ{=D=G} src.aq, dst.wl 0 3E MOVAW src.aw, dst.wl 0 9F PUSHAB src.ab, {-(SP).wl} 2+1w DF PUSHAL{=F} src.al, {-(SP).wl} 2+1w 7F PUSHAQ{=D=G} src.aq, {-(SP).wl} 2+1w 3F PUSHAW src.aw, {-(SP).wl} 2+1w CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 149 CVAX INSTRUCTION TIMING 12.2.3 Variable Length Bit Field Instructions - Opcode Instruction Execution Cycles ------ ----------- ---------------- EC CMPV pos.rl, size.rb, base.vb, 12-18, 13 typ v = reg {field.rv}, src.rl 11+1r - 14+2r, 12+1r typ v = mem ED CMPZV pos.rl, size.rb, base.vb, 12-18, 13 typ v = reg {field.rv}, src.rl 11+1r - 14+2r, 12+1r typ v = mem EE EXTV pos.rl, size.rb, base.vb, 12-18, 13 typ v = reg {field.rv}, dst.wl 11+1r - 14+2r, 12+1r typ v = mem EF EXTZV pos.rl, size.rb, base.vb, 12-18, 13 typ v = reg {field.rv}, dst.wl 11+1r - 14+2r, 12+1r typ v = mem F0 INSV src.rl, pos.rl, size.rb, base.vb, 10-12, 10 typ v = reg {field.wv} 13+1r+1w - 15+2r+2w, 13+1r+1w typ v = mem EB FFC startpos.rl, size.rb, base.vb, 14-36, 21 typ v = reg {field.rv}, findpos.wl 13+1r - 37+2r, 23+1r typ v = mem EA FFS startpos.rl, size.rb, base.vb, 13-35, 20 typ v = reg {field.rv}, findpos.wl 12+1r - 36+2r, 22+1r typ v = mem 12.2.4 Control Instructions - The number before the slash is cycles for branch not taken, after the slash for branch taken. If the opcode and first specifier of the instruction at the branch target of a taken branch overlap a longword boundary, add 1r cycle to the branch taken execution time. Opcode Instruction Execution Cycles ------ ----------- ---------------- 9D ACBB limit.rb, add.rb, index.mb, displ.bw 8/8+1r index = reg 6/6+1r index = mem F1 ACBL limit.rl, add.rl, index.ml, displ.bw 8/8+1r index = reg 6/6+1r index = mem 3D ACBW limit.rw, add.rw, index.mw, displ.bw 8/8+1r index = reg 6/6+1r index = mem F3 AOBLEQ limit.rl, index.ml, displ.bb 5/5+1r index = reg 4/4+1r index = mem F2 AOBLSS limit.rl, index.ml, displ.bb 5/5+1r index = reg 4/4+1r index = mem 1E BCC{=BGEQU} displ.bb 1/3+1r 1F BCS{=BLSSU} displ.bb 1/3+1r CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 150 CVAX INSTRUCTION TIMING 13 BEQL{=BEQLU} displ.bb 1/3+1r 18 BGEQ displ.bb 1/3+1r 14 BGTR displ.bb 1/3+1r 1A BGTRU displ.bb 1/3+1r 15 BLEQ displ.bb 1/3+1r 1B BLEQU displ.bb 1/3+1r 19 BLSS displ.bb 1/3+1r 12 BNEQ{=BNEQU} displ.bb 1/3+1r 1C BVC displ.bb 1/3+1r 1D BVS displ.bb 1/3+1r E1 BBC pos.rl, base.vb, displ.bb, {field.rv} 5/7+1r v = reg 6+1r/8+2r v = mem E0 BBS pos.rl, base.vb, displ.bb, {field.rv} 5/7+1r v = reg 6+1r/8+2r v = mem E5 BBCC pos.rl, base.vb, displ.bb, {field.mv} 6/8+1r v = reg 7+1r+1w/7+2r+1w v = mem E3 BBCS pos.rl, base.vb, displ.bb, {field.mv} 6/8+1r v = reg 7+1r+1w/7+2r+1w v = mem E4 BBSC pos.rl, base.vb, displ.bb, {field.mv} 6/8+1r v = reg 7+1r+1w/7+2r+1w v = mem E2 BBSS pos.rl, base.vb, displ.bb, {field.mv} 6/8+1r v = reg 7+1r+1w/7+2r+1w v = mem E7 BBCCI pos.rl, base.vb, displ.bb, {field.mv} 6/8+1r v = reg 7+1r+1w/9+2r+1w v = mem E6 BBSSI pos.rl, base.vb, displ.bb, {field.mv} 6/8+1r v = reg 7+1r+1w/9+2r+1w v = mem E9 BLBC src.rl, displ.bb 2/4+1r E8 BLBS src.rl, displ.bb 2/4+1r 11 BRB displ.bb 3+1r 31 BRW displ.bw 3+1r 10 BSBB displ.bb, {-(SP).wl} 4+1r+1w 30 BSBW displ.bw, {-(SP).wl} 4+1r+1w 8F CASEB selector.rb, base.rb, limit.rb, 8+2r/7+1r displ.bw-list CF CASEL selector.rl, base.rl, limit.rl, 8+2r/7+1r displ.bw-list AF CASEW selector.rw, base.rw, limit.rw, 8+2r/7+1r displ.bw-list 17 JMP dst.ab 3+1r 16 JSB dst.ab, {-(SP).wl} 4+1r+1w 05 RSB {(SP)+.rl} 4+2r F4 SOBGEQ index.ml, displ.bb 4/4+1r index = reg 3/3+1r index = mem CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 151 CVAX INSTRUCTION TIMING F5 SOBGTR index.ml, displ.bb 4/4+1r index = reg 3/3+1r index = mem 12.2.5 Procedure Call Instructions - In this section, n = number of set register bits in the procedure call mask. The register writes in CALLx are timed for every other cycle; if the external memory subsystem cannot keep pace, there will be additional stalls for the memory delays. The last five writes are timed for every third cycle; if the external memory subsystem cannot keep pace, there will be additional stalls for memory delays. Opcode Instruction Execution Cycles ------ ----------- ---------------- FA CALLG arglist.ab, dst.ab, {-(SP).w*} 21+2r+5w+n+nw FB CALLS numarg.rl, dst.ab, {-(SP).w*} 24+2r+6w+n+nw 04 RET {(SP)+.r*} 13+5r+nr from G 15+6r+nr from S 12.2.6 Miscellaneous Instructions - In this section, n = leftmost set bit in the register mask. The writes in PUSHR are timed for every third cycle; if the external memory subsystem cannot keep pace, there will be additional stalls for memory delays. Opcode Instruction Execution Cycles ------ ----------- ---------------- B9 BICPSW mask.rw 5 B8 BISPSW mask.rw 5 03 BPT {-(KSP).w*} exception 00 HALT {-(KSP).w*} 2 0A INDEX subscript.rl, low.rl, high.rl, 39 size.rl, indexin.rl, indexout.wl DC MOVPSL dst.wl 2 dst = reg 1 dst = mem 01 NOP 1 BA POPR mask.rw, {(SP)+.r*} 8+n+nr BB PUSHR mask.rw, {-(SP).w*} 5+2n+nw CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 152 CVAX INSTRUCTION TIMING FC XFC {unspecified operands} exception 12.2.7 Queue Instructions - Opcode Instruction Execution Cycles ------ ----------- ---------------- 5C INSQHI entry.ab, header.aq 19+3r+5w 5D INSQTI entry.ab, header.aq 20+4r+6w 0E INSQUE entry.ab, pred.ab 5+2r+4w 5E REMQHI header.aq, addr.wl 17+4r+3w 5F REMQTI header.aq, addr.wl 21+5r+4w 0F REMQUE entry.ab, addr.wl 7+3r+2w 12.2.8 Character String Instructions - For CMPC3, CMPC5, LOCC, SKPC, SCANC, SPANC, n = characters processed in main loop; k = characters processed in fill loop. For MOVC3, MOVC5, n = LONGWORDS processed in main loop; k = LONGWORDS procsessed in fill loop. Opcode Instruction Execution Cycles ------ ----------- ---------------- 29 CMPC3 len.rw, src1addr.ab, src2addr.ab 6+6n+2nr 2D CMPC5 src1len.rw, src1addr.ab, fill.rb, 6+6n+2nr+3k+kr src2len.rw, src2addr.ab 3A LOCC char.rb, len.rw, addr.ab 5+3n+nr 28 MOVC3 len.rw, srcaddr.ab, dstaddr.ab 16+3n+nr+nw 2C MOVC5 srclen.rw, srcaddr.ab, fill.rb, 26+3n+nr+nw+2k+kw dstlen.rw, dstaddr.ab 2A SCANC len.rw, addr.ab, tbladdr.ab, mask.rb 6+4n+2nr 3B SKPC char.rb, len.rw, addr.ab 5+3n+nr 2B SPANC len.rw, addr.ab, tbladdr.ab, mask.rb 6+4n+2nr CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 153 CVAX INSTRUCTION TIMING 12.2.9 Operating System Support Instructions - The writes in SVPCTX are timed for every third cycle; if the external memory subsystem cannot keep pace, there will be additional stalls for memory delays. Opcode Instruction Execution Cycles ------ ----------- ---------------- BD CHME param.rw, {-(ySP).w*} 26+2r+3w BC CHMK param.rw, {-(ySP).w*} 26+2r+3w BE CHMS param.rw, {-(ySP).w*} 26+2r+3w BF CHMU param.rw, {-(ySP).w*} 26+2r+3w Where y=MINU(x, PSL) 06 LDPCTX {PCB.r*, -(KSP).w*} 17+22r+2w DB MFPR procreg.rl, dst.wl 5-12, 11 typ DA MTPR src.rl, procreg.rl 8-12, 11 typ 0C PROBER mode.rb, len.rw, base.ab 13-14, 13 typ 0D PROBEW mode.rb, len.rw, base.ab 13-14, 13 typ 02 REI {(SP)+.r*} 22+2r - 33+2r, 24+2r typ 07 SVPCTX {(SP)+.r*, PCB.w*} 6+2r+20w - 12+2r+20w, 12+2r+20w typ 12.2.10 Floating Point Instructions - Opcode Instruction Execution Cycles ------ ----------- ---------------- 6F ACBD limit.rd, add.rd, index.md,displ.bw tbd 4F ACBF limit.rf, add.rf, index.mf,displ.bw tbd 4FFD ACBG limit.rg, add.rg, index.mg,displ.bw tbd 60 ADDD2 add.rd, sum.md tbd 40 ADDF2 add.rf, sum.mf tbd 40FD ADDG2 add.rg, sum.mg tbd 61 ADDD3 add1.rd, add2.rd, sum.wd tbd 41 ADDF3 add1.rf, add2.rf, sum.wf tbd 41FD ADDG3 add1.rg, add2.rg, sum.wg tbd 71 CMPD src1.rd, src2.rd tbd 51 CMPF src1.rf, src2.rf tbd 51FD CMPG src1.rg, src2.rg tbd 6C CVTBD src.rb, dst.wd tbd 4C CVTBF src.rb, dst.wf tbd CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 154 CVAX INSTRUCTION TIMING 4CFD CVTBG src.rb, dst.wg tbd 68 CVTDB src.rd, dst.wb tbd 76 CVTDF src.rd, dst.wf tbd 6A CVTDL src.rd, dst.wl tbd 69 CVTDW src.rd, dst.ww tbd 48 CVTFB src.rf, dst.wb tbd 56 CVTFD src.rf, dst.wd tbd 99FD CVTFG src.rf, dst.wg tbd 4A CVTFL src.rf, dst.wl tbd 49 CVTFW src.rf, dst.ww tbd 48FD CVTGB src.rg, dst.wb tbd 33FD CVTGF src.rg, dst.wf tbd 4AFD CVTGL src.rg, dst.wl tbd 49FD CVTGW src.rg, dst.ww tbd 6E CVTLD src.rl, dst.wd tbd 4E CVTLF src.rl, dst.wf tbd 4EFD CVTLG src.rl, dst.wg tbd 6D CVTWD src.rw, dst.wd tbd 4D CVTWF src.rw, dst.wf tbd 4DFD CVTWG src.rw, dst.wg tbd 6B CVTRDL src.rd, dst.wl tbd 4B CVTRFL src.rf, dst.wl tbd 4BFD CVTRGL src.rg, dst.wl tbd 66 DIVD2 divr.rd, quo.md tbd 46 DIVF2 divr.rf, quo.mf tbd 46FD DIVG2 divr.rg, quo.mg tbd 67 DIVD3 divr.rd, divd.rd, quo.wd tbd 47 DIVF3 divr.rf, divd.rf, quo.wf tbd 47FD DIVG3 divr.rg, divd.rg, quo.wg tbd 74 EMODD mulr.rd, mulrx.rb, muld.rd, int.wl, tbd fract.wd 54 EMODF mulr.rf, mulrx.rb, muld.rf, int.wl, tbd fract.wf 54FD EMODG mulr.rg, mulrx.rw, muld.rg, int.wl, tbd fract/wg 72 MNEGD src.rd, dst.wd tbd 72 MNEGD src.rd, dst.wd tbd 52FD MNEGG src.rg, dst.wg tbd 70 MOVD src.rd, dst.wd tbd 50 MOVF src.rf, dst.wf tbd 50FD MOVG src.rg, dst.wg tbd 64 MULD2 mulr.rd, prod.md tbd 44 MULF2 mulr.rf, prod.mf tbd 44FD MULG2 mulr.rg, prod.mg tbd 65 MULD3 mulr.rd, muld.rd, prod.wd tbd 45 MULF3 mulr.rf, muld.rf, prod.wf tbd CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 155 CVAX INSTRUCTION TIMING 45FD MULG3 mulr.rg, muld.rg, prod.wg tbd 75 POLYD arg.rd, degree.rw, table.ab tbd 55 POLYF arg.rf, degree.rw, table.ab tbd 55FD POLYG arg.rf, degree.rw, table.ab tbd 62 SUBD2 sub.rd, dif.md tbd 42 SUBF2 sub.rf, dif.mf tbd 42FD SUBG2 sub.rg, dif.mg tbd 63 SUBD3 sub.rd, min.rd, dif.wd tbd 43 SUBF3 sub.rf, min.rf, dif.wf tbd 43FD SUBG3 sub.rg, min.rg, dif.wg tbd 73 TSTD src.rd tbd 53 TSTF src.rf tbd 53FD TSTG src.rg tbd 12.2.11 Microcode-Assisted Emulated Instructions - The times gives here are for execution of the emulation exception. Opcode Instruction Execution Cycles ------ ----------- ---------------- 20 ADDP4 addlen.rw, addaddr.ab, sumlen.rw, 17+2r+10w sumaddr.ab 21 ADDP6 add1len.rw, add1addr.ab, add2len.rw, 17+2r+10w add2addr.ab, sumlen.rw, sumaddr.ab F8 ASHP cnt.rb, srclen.rw, srcaddr.ab, round.rb, 17+2r+10w dstlen.rw, dstaddr.ab 35 CMPP3 len.rw, src1addr.ab, src2addr.ab 17+2r+10w 37 CMPP4 src1len.rw, src1addr.ab, src2len.rw, 17+2r+10w src2addr.ab 0B CRC tbl.ab, inicrc.rl, strlen.rw, stream.ab 17+2r+10w F9 CVTLP src.rl, dstlen.rw, dstaddr.ab 17+2r+10w 36 CVTPL srclen.rw, srcaddr.ab, dst.wl 17+2r+10w 08 CVTPS srclen.rw, srcaddr.ab, dstlen.rw, 17+2r+10w dstaddr.ab 09 CVTSP srclen.rw, srcaddr.ab, dstlen.rw, 17+2r+10w dstaddr.ab 24 CVTPT srclen.rw, srcaddr.ab, tbladdr.ab, 17+2r+10w dstlen.rw, dstaddr.ab 26 CVTTP srclen.rw, srcaddr.ab, tbladdr.ab, 17+2r+10w dstlen.rw, dstaddr.ab 27 DIVP divrlen.rw, divraddr.ab, divdlen.rw, 17+2r+10w CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 156 CVAX INSTRUCTION TIMING divdaddr.ab, quolen.rw, quoaddr.ab 38 EDITPC srclen.rw, srcaddr.ab, pattern.ab, 17+2r+10w dstaddr.ab 39 MATCHC objlen.rw, objaddr.ab, srclen.rw, 17+2r+10w srcaddr.ab 34 MOVP len.rw, srcaddr.ab, dstaddr.ab 17+2r+10w 2E MOVTC srclen.rw, srcaddr.ab, fill.rb, 17+2r+10w tbladdr.ab, dstlen.rw, dstaddr.ab 2F MOVTUC srclen.rw, srcaddr.ab, esc.rb, 17+2r+10w tbladdr.ab, dstlen.rw, dstaddr.ab 25 MULP mulrlen.rw, mulraddr.ab, muldlen.rw, 17+2r+10w muldaddr.ab, prodlen.rw, prodaddr.ab 22 SUBP4 sublen.rw, subaddr.ab, diflen.rw, 17+2r+10w difaddr.ab 23 SUBP6 sublen.rw, subaddr.ab, minlen.rw, 17+2r+10w minaddr.ab, diflen.rw, difaddr.ab CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 157 CVAX INSTRUCTION TIMING 12.3 Other Timings Event Execution Cycles ------ ---------------- initiate hardware interrupt 20+3r+2w initiate software interrupt 24+2r+2w - 40+2r+2w, 30+2r+2w typ initiate exception 30+2r+2w - 50+2r+8w, 35+2r+3w typ unaligned read operand (word or longword) 1r unaligned read operand (quadword) 2r unaligned write operand (word or longword) 1+1w unaligned write operand (quadword) 2+2w TB miss, system space 4+1r TB miss, process space, single miss 6+1r TB miss, process space, double miss 11+2r I stream fetch delay after TB miss 5+1r Branch displacement fetch delay after TB miss 7+1r M bit clear, system space 9+2r+1w M bit clear, process space, single miss 9+2r+1w M bit clear, process space, double miss 17+3r+1w Read crossing page boundary 8 Write crossing page boundary 7+2r DMA latency 3 interrupt latency tbd CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 158 CVAX INSTRUCTION TIMING 12.4 Examples ADDL2 d(r),r - aligned memory operand, cache hit, no TB miss specifier 1 time 1+1r specifier 2 time 0 execute, fetch time 1 ---- total 2+1r MOVL r,d(r) - aligned memory operand, cache hit, no TB miss specifier 1 time 1 specifier 2 time 1+1w execute, fetch time 0 ---- total 2+1w SOBLEQ r,disp - cache hit, no TB miss, instruction at branch target spans a longword boundary specifier 1 time 1 (note - 1 specifier) execute, fetch time 4+1r (note - branch taken) unaligned new instruction 1r ---- total 5+2r INDEX d(r),@d(r),(r)[rx],@(r)+,-(r),@d(r)[rx] - all memory operands unaligned across page boundaries, all memory operands take TB misses on both reads, M bit clear, cache hits specifier 1 time 1+1r specifier 1 cross page 8 specifier 1 TB miss x 2 12+2r specifier 1 unaligned 1r specifier 2 time 1+2r specifier 2 cross page x 2 16 specifier 2 TB miss x 4 24+4r specifier 2 unaligned x 2 2r specifier 3 time 2+1r specifier 3 cross page 8 specifier 3 TB miss x 2 12+2r specifier 3 unaligned 1r specifier 4 time 2+2r specifier 4 cross page x 2 16 specifier 4 TB miss x 4 24+4r specifier 4 unaligned x 2 2r specifier 5 time 2+1r specifier 5 cross page 8 specifier 5 TB miss x 2 12+2r specifier 5 unaligned 1r specifier 6 time 3+1r+1w specifier 6 read cross page 8 CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 159 CVAX INSTRUCTION TIMING specifier 6 write cross page 7+2r specifier 6 TB miss x 4 24+4r specifier 6 M bit clear x 2 18+4r+2w specifier 6 read unaligned 1r specifier 6 write unaligned 1+1w execute, fetch time 39 ---- total 248+38r+4w