






















                            ESS MASTER CARD

                               26 MAY 81

                              REVISION 3.1

                                88000106

                    DIRECT COMMENTS TO DAVE WOTRING

                 THIS DOCUMENT REFLECTS THE REV 01 PCB

























.PA



                           TABLE OF CONTENTS



1.0 INTRODUCTION

2.0  HARDWARE DESCRIPTION

     2.1       Z80 CPU MODULE

     2.1.1     WAIT STATE GENERATOR

     2.2       INTERRUPT CONTROLLER

     2.3       TIMING CONTROLLER

     2.4       ASYNCHRONOUS SERIAL INTERFACE

     2.5       GPIB (IEEE 488) INTERFACE

     2.6       DYNAMIC RAM MEMORY

     2.7       BOOT PROM/DIAGNOSTIC MONITOR

     2.8       MASTER BUS CONTROLLER

     2.9       CONTROL PORT

     2.10      DIRECT MEMORY ACCESS CONTROLLER

     2.11      HIGH SPEED PARALLEL INTERFACE TO ACORN

     2.12      CONFIGURATION SWITCH PORT

3.0 MEMORY AND I/O MAP

     3.1       MEMORY MAP

     3.2       I/O ADDRESS MAP

4.0 ESS MASTER CARD CHECKOUT PROCEDURE

5.0 DESCRIPTION OF SYSTEM BOOT/DIAGNOSTIC MONITOR PROGRAM

6.0 JUMPER OPTIONS ON ESS MASTER

     6.1       JUMPERS

     6.2       TERMINALS

     6.3       TEST POINTS

7.0 CONNECTORS

     7.1       MASTERBUS P1

     7.2       MASTERBUS P2

     7.3       HIP INTERFACE (ACORN I/O EXPANDER)

8.0 MESSAGES

     8.1       MESSAGES RECEIVED

     8.2       MESSAGES TRANSMITTED



             APPENDICIES OF PROGRAMMABLE PARTS DATA SHEETS

A    AMD 9519 INTERRUPT CONTROLLER

B    AMD 9513 SYSTEM TIMER

C    TI 9914 GPIB (IEEE 488) CONTROLLER

D    Z80 DUART

E    AMD 9517 DIRECT MEMORY ACCESS CONTROLLER





                       OTHER APPLICABLE DOCUMENTS

EIA RS232C SPECIFICATION

IEEE 488-1978 SPECIFICATION

EIA RS449 SPECIFICATION

EIA RS422 SPECIFICATION

EIA RS423 SPECIFICATION

.PA







1.0 INTRODUCTION

     The  ESS  master  card controls the  emulation  hardware.  The  ESS

master's control program is downloaded from a host computer via the GPIB

interface  or one of the serial ports or link to HIP processor.  The ESS

master card has the following features:

     -the P1 connector is ESS MASTERBUS compatable

     -4MHz Z80 CPU

     -16 channel priority interrupt controller

     -two RS232 serial ports 110 baud to 19.2K baud (DCE)

     -one RS232 serial port 110 baud to 19.2K baud (DTE)

     -one RS449 serial port 110 baud to 750K baud (DTE)

     -one GPIB (IEEE 488) interface

     -four channel DMA controller

     -32K byte expandable to 48K byte dynamic memory with parity

     -2K byte BOOT PROM/diagnostic monitor

     -high speed parallel interface to HIP processor

     -six timer interrupts







2.0  HARDWARE DESCRIPTION (see block diagram)



     2.1  Z80 CPU MODULE

          The  Z80 CPU  module consists of a Z80 CPU running at 4MHz and

buffers for the processors address and data bus.  Gates are provided  to

generate IOWR,IORD,MWR,MRD,RFSH and INTACK strobes.  This module has one

I/O port .  The address expansion port is read/write. This port is reset

to  0 at power on.  The address extension port provides addresses AE-A13

to  the MASTER BUS
whe                                                                             
                                                    BUS

     B6   address A12 to MASTER BUS

     B5   address A11 to MASTER BUS

     B4   address A10 to MASTER BUS

     B3   address AF  to MASTER BUS

     B2   address AE  to MASTER BUS

     B1   not used

     B0   not used



     2.1.1 WAIT STATE GENERATOR



          The wait state generator works as follows.  The WAIT flip-flop

is  set on each memory or I/O access.  When the accessed device responds

with an acknowlege the WAIT flip-flop will be cleared removing the  wait

from  the processor.  The same signal that sets the WAIT flip-flop  will

also  trigger  a retriggerable one-shot.  If the one-shot times out  the

WAIT flip-flop will be cleared and an interrupt will be generated to the

processor.  The Z80 processor will receive one wait state on each memory

access. The DMA controller will receive one wait state on each read from

memory,write  to  a peripheral and two wait states on each read  from  a

peripheral,write to memory cycle.





     2.2 INTERRUPT CONTROLLER MODULE



          The  interrupt  controller module is capable of  accepting  16

interrupt inputs.  The controller will consist of two AMD 9519 interrupt

controllers.  The  controller will be programmed to respond to a  rising

edge as an interrupt request.  An interrupt request must last for  300nS

minimum  to be recognized.  To program the interrupt controller see  the

9519 data sheet. The interrupt inputs and their priorities are as follows.



     INTERRUPT

     NMI       not assigned

     0         memory parity error

     1         bus access timeout

     2         GPIB (IEEE488) interface

     3         high speed parallel interface to HIP

     4         serial interrupt 0 (RS449 and RS232 DTE)

     5         serial interrupt 1 (RS232 and RS232 DCE)

     6         DMA controller

     7         timer 0 (100mS)

     8         alternate ESS not assigned

     9         timer 1

    10         timer 3

    11         timer 4

    12         Emulation SubSystem

    13         timer 5

    14         timer 2

    15         not assigned



.PA

     2.3 TIMING CONTROLLER MODULE



          The  timing  controller module consists of a 24MHz  and  20MHz

master oscillators and an AMD 9513 system timing controller.



          2.3.1 20MHz OSCILLATOR



          The  20MHz will be divided down to provide (1) 10MHz for  CCLK

MASTER BUS signal, (2) 5MHz for the 9914 GPIB controller and 9513 timer.



          2.3.2 24MHz OSCILLATOR



          The 24MHz oscillator will provide (1) 24MHz to the 8202 memory

controller and will be divided down to provide 4MHz for the Z80 and 9517

DMA  controller.  The 24MHz oscillator is also divided down  to  provide

6MHz for the baud rate generator.



          2.3.3 9513 SYSTEM TIMING CONTROLLER



          Two  9513  system timing controllers are used to generate  the

system  time intervals.  Bit B6 in the control port is used to switch  a

mux  to connect the BAUD 1-4 outputs of timer 0 to timer interrupts  1-4

for testing. To program this device see the 9513 data sheet.



     INPUTS TO THE TIMER

     F1        1MHz

     F2        100KHz

     F3        10KHz

     F4        1KHz

     F5        100Hz

     SOURCE 1  6MHz

     SOURCE 2  5MHz

     SOURCE 3  4MHz

     SOURCE 4  3MHz

     SOURCE 5  2MHz



     OUTPUTS FROM THE TIMER

     TIMER 0

     OUT1      BAUD 1 RS449 (DTE) SERIAL PORT

     OUT2      BAUD 2 RS232 (DTE) SERIAL PORT

     OUT3      BAUD 3 RS232 (DCE) 1 SERIAL PORT

     OUT4      BAUD 4 RS232 (DCE) 2 SERIAL PORT

     OUT5      TIMER INTERRUPT 0 (100mS interval)

     TIMER 1

     OUT1      TIMER INTERRUPT 1

     OUT2      TIMER INTERRUPT 2

     OUT3      TIMER INTERRUPT 3

     OUT4      TIMER INTERRUPT 4

     OUT5      TIMER INTERRUPT 5







.pa

     2.4 ASYNCHRONOUS COMMUNICATION INTERFACE



          The asynchronous communications interface consists of two  Z80

DUART  communication
c                                                                               
                                                 rom  110  baud to 750K baud.
The baud rate generator is  an  AMD  9513

system  timing controller.  This interface has an 8 bit input port which

is used to configure the baud rate for one of the ports.  UART0  channel

'A'  is  the RS449 (DTE) port and channel 'B' is the RS232  (DTE)  port.

UART1  channel  'A' is an RS232 (DCE) port and channel 'B' is  an  RS232

(DCE)  port.  The  RS449  and RS232 DTE ports are connected to  the  DMA

controller.



     The following signals are present at the RS449 connector.



     PIN

     19   SG                  SIGNAL GROUND

     37   SC                  SEND COMMON

     20   RC                  RECEIVE COMMON

     17   TT   OUTPUT TO DCE  TERMINAL TIMING

     35   TT'

     12   TR   OUTPUT TO DCE  TERMINAL READY

     30   TR'

     11   DM   INPUT FROM DCE DATA MODE

     29   DM'

      4   SD   OUTPUT TO DCE  SEND DATA

     22   SD'

      6   RD   INPUT FROM DCE RECEIVE DATA

     24   RD'

      5   ST   INPUT FROM DCE SEND TIMING

     23   ST'

      8   RT   INPUT FROM DCE RECEIVE TIMING

     26   RT'

      7   RS   OUTPUT TO DCE  REQUEST TO SEND

     25   RS'

      9   CS   INPUT FROM DCE CLEAR TO SEND

     27   CS'

     13   RR   INPUT FROM DCE RECEIVER READY

     31   RR'



     The following signals are present at the RS232 connector.



     PIN

      1

      2   XMIT DATA  INPUT TO DCE       TRANSMITTED DATA

      3   RCV DATA   OUTPUT FROM DCE    RECEIVED DATA

      4   RTS        INPUT TO DCE       REQUEST TO SEND

      5   CTS        OUTPUT FROM DCE    CLEAR TO SEND

      6   DSR        OUTPUT FROM DCE    DATA SET READY

      7   GND                           SIGNAL GROUND

      8   DCD        OUTPUT FROM DCE    DATA CARRIER DETECT

     20   DTR        INPUT TO DCE       DATA TERMINAL READY



.PA



     The  baud rate select input port is configured as  follows.  OFF=1.

     The maximum RS232 rate is 19.2K baud.



                       SW2

     RS449 RATE (DTE)   ! RS232 RATE (DTE)

     BIT7 BIT6 BIT5 BIT4! BIT3 BIT2 BIT1 BIT0 BAUD

     SW8  SW7  SW6  SW5 ! SW4  SW3  SW2  SW1

     OFF  OFF  OFF  OFF ! OFF  OFF  OFF  OFF  110     -!

     OFF  OFF  OFF  ON  ! OFF  OFF  OFF  ON   300      !

     OFF  OFF  ON   OFF ! OFF  OFF  ON   OFF  600      !

     OFF  OFF  ON   ON  ! OFF  OFF  ON   ON   1200     !

     OFF  ON   OFF  OFF ! OFF  ON   OFF  OFF  2400     !RS232 RATE

     OFF  ON   OFF  ON  ! OFF  ON   OFF  ON   4800     !

     OFF  ON   ON   OFF ! OFF  ON   ON   OFF  9600     !

     OFF  ON   ON   ON  ! OFF  ON   ON   ON   19.2K   _!

     ON   OFF  OFF  OFF ! ON   OFF  OFF  OFF  38.4K

     ON   OFF  OFF  ON  ! ON   OFF  OFF  ON   56K

     ON   OFF  ON   OFF ! ON   OFF  ON   OFF  134.5

     ON   OFF  ON   ON  ! ON   OFF  ON   ON   150

     ON   ON   OFF  OFF ! ON   ON   OFF  OFF  76.8K

     ON   ON   OFF  ON  ! ON   ON   OFF  ON   187.5K

     ON   ON   ON   OFF ! ON   ON   ON   OFF  375K

     ON   ON   ON   ON  ! ON   ON   ON   ON   750K



     BAUD RATE DIVISOR PROGRAMMING TABLE



The master mode register of timer 0 is programmed to 8000H

BRATE   CALCULATED  TIME ACTUAL     COUNTER MODE  INPUT DIVISOR

        16X CLOCK    uS  16X CLOCK  CTRL REG      FREQ  LOAD REG

110     1760        568  1760.56    0533H         2MHZ  0568H

134.5   2152        464  2152.08    0133H         6MHZ  1394H

150     2400        416  2400       0133H         6MHZ  1250H

300     4800        208  4800       0133H         6MHZ  0625H

600     9600        104  9615.38    0B33H         1MHZ  0052H

1200    19200       52   19230.7    0B33H         1MHZ  0026H

2400    38400       26   38461.5    0B33H         1MHZ  0013H

4800    76800       13   76923.07   0333H         4MHZ  0026H

9600    153600      6.5  153846.15  0333H         4MHZ  0013H

19.2K   307200      3.2  312500     0233H         5MHZ  0008H

38.4K   614400      1.6  625000     0233H         5MHZ  0004H

56K     896000
1                                                                               
                                                 CK    5.3  187500     0133H
    6MHZ  0016H

375K    X1 CLOCK    2.6  375000     0133H         6MHZ  0008H

750K    X1 CLOCK    1.33 750000     0133H         6MHZ  0004H

100MS INTERVAL           10HZ       0F33H         100HZ 0005H



.PA

     2.5  GPIB (IEEE 488) CONTROLLER



          The GPIB controller will consist of a TI 9914 GPIB  controller

and  75160,75161 GPIB interface chips.  This interface will connect to a

DMA channel.  This interface will also have an 8 bit input port which is

read  at  power on to set the address of the GPIB.  An  option  will  be

provided to replace the 75161 interface chip with a 75162 interface chip

to allow controller capability on the GPIB bus.  See the 9914 data sheet

for programming instructions. Note that the non address bits in the GPIB

address  port must be masked off (to 0) before loading the 9914  address

register.



     BACK PANEL SWITCH PORT

     BIT7 BSW2      BACK PANEL BAUD SW2  !

     BIT6 BSW1      BACK PANEL BAUD SW1  !SEE RS232 RATES SW2

     BIT5 BSW0      BACK PANEL BAUD SW0  !

     BIT4 GSW5      GPIB ADDRESS BIT 5,OFF=0 ON=1

     BIT3 GSW4      GPIB ADDRESS BIT 4,OFF=0 ON=1

     BIT2 GSW3      GPIB ADDRESS BIT 3,OFF=0 ON=1

     BIT1 GSW2      GPIB ADDRESS BIT 2,OFF=0 ON=1

     BIT0 GSW1      GPIB ADDRESS BIT 1,OFF=0 ON=1





     2.6  DYNAMIC MEMORY

          The  memory is a 32K byte expandable to 48K byte with  parity.

The  memory  will use the Intel 8202 controller and 2118  16Kx1  dynamic

RAMS.  The memory access time is 600nSec for an M1 cycle and 750nSec for

M2-M5.  The memory will cause one wait state to be inserted for each Z80

access  or  DMA  write to peripheral access.  Two wait  states  will  be

inserted for DMA read from peripheral accesses.



     2.7  BOOT/DIAGNOSTIC MONTIOR PROM

          The  BOOT/Diagnostic  monitor will live in a  2716/2732  EPROM

located in the first 2K (2716),4K (2732) bytes of the memory  space.  An

option  is provided to accommodate two 2716 or 2732 EPROMs expanding the

boot memory space to 8K bytes.The BOOT prom is enabled by power on reset

or clearing a bit in the control port. The boot prom will shadow the RAM

memory  for  memory reads when enabled.  When the BOOT PROM  is  enabled

memory  parity errors are inhibited for the address space the BOOT  PROM

overlays. The LED status port is reset to 0 at power on turning the LEDs

on. Writing a 1 to a bit position in the LED port will turn the led off.



     LED STATUS PORT BIT DEFINITIONS

     BIT7 LED7      RAM 32-48K OK

     BIT6 LED6      OTHER PORTS OK

     BIT5 LED5      DMA MEMORY TO MEMORY XFER OK

     BIT4 LED4      RAM 0-16K OK

     BIT3 LED3      RAM 16K-32K OK

     BIT2 LED2      TIMER OK

     BIT1 LED1      STACK RAM OK

     BIT0 LED0      BOOT CHECKSUM OK

.PA



     2.8  MASTER BUS CONTROLLER



          The  MASTER BUS controller consists of tristate buffers and  a

sequencer  which  will cause MASTER BUS memory requests when the Z80  or

DMA  controller  access memory locations  C000H-FFFFH.  MASTER  BUS  I/O

requests are generated when the Z80 accesses I/O devices with an address

greater than 60H.



     2.9  CONTROL PORT



          The control port is an 8 bit read/write port.



     BIT

     7    0=BOOT prom enabled ,1=BOOT prom disabled

     6    1= connect baud 1-4 to timer interrupt 1-4

     5    1= enable DMA request from RS449 (DTE) port

     4    1= local I/O device reset

     3    1= MASTER BUS reset

     2    1= enable DMA request from RS232 (DTE) port

     1    0= DISABLE NMI

     0    1= WRAP BACK SERIAL DATA

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     2.10 DIRECT MEMORY ACCESS CONTROLLER



          The  direct  memory access controller consists of an AMD  9517

DMA controller and  an address extension  port to extend the address  to

20  bits.  The DMA controller will request the bus from the Z80 when  it

receives  a  DMA request and will
release                                                                         
                                                       ndshake with the
following  devices:  GPIB,RS449,HIP

LINK,RS232 (DTE).  The address extension port is read/write. The address

extension  port is reset to 0 at power on.  The address  extension  port

provides  addresses  AE-A13  to the MASTER BUS when the  DMA  controller

accesses memory locations C000H-FFFFH.



     DMA address extension port

     B7   address A13 to MASTER BUS

     B6   address A12 to MASTER BUS

     B5   address A11 to MASTER BUS

     B4   address A10 to MASTER BUS

     B3   address AF  to MASTER BUS

     B2   address AE  to MASTER BUS

     B1   not used

     B0   not used



     2.11 PARALLEL LINK TO ACORN

          The  parallel  link  to  HIP will connect  to  the  ACORN  I/O

expansion connector.  The device is capable of interrupting both the HIP

and the ESS processor. The device is capable of operating DMA to the ESS

memory.  The  device  used for this interface is a Z80  PIO  located  at

address 40-43H in the HIP processors I/O address space.  The 'A' port is

programmed in mode 2 (bidirectional hand shake) and the 'B' port in mode

3 as input only.  Bit 0 of port 'B' when 1 means there is a character in

the output buffer for the ESS. Bit 7 of port 'B' when 1 means there is a

character  in  the  input buffer for the HIP.  On the ESS  side  of  the

interface the data port is 18H and the command status port is 56H.



     HIP LINK COMMAND STATUS PORT (READ/WRITE)

     B7   1= OBF (CHARACTER FOR HIP IN OUT BUFFER) READ ONLY

     B6   not defined

     B5   not defined

     B4   1= ENABLE OBF DMA REQUESTS

     B3   1= ENABLE IBF DMA REQUESTS

     B2   1= ENABLE OBF INTERRUPT REQUESTS

     B1   1= ENABLE IBF INTERRUPT REQUESTS

     B0   1= IBF (CHARACTER FOR ESS IN INPUT BUFFER) READ ONLY

.PA



     2.12 CONFIGURATION SWITCH PORT

          The   configuration   switch   port  identifies   the   system

configuration and the boot from device.



     CONFIGURATION SWITCH PORT SW1

     BIT7 SW8  OFF=0 32K MEMORY ON=1 48K MEMORY

     BIT6 SW7

     BIT5 SW6

     BIT4 SW5

     BIT3 SW4  ON=1 USE 7BIT LINK PROTOCOL

     BIT2 SW3 BIT1 SW2  BIT0 SW1

          OFF      OFF       OFF   BOOT FROM GPIB

          OFF      OFF       ON    BOOT FROM RS449

          OFF      ON        OFF   BOOT FROM HIP INTERFACE

          OFF      ON        ON    BOOT FROM RS232 (DTE)

          ON       OFF       OFF   BOOT FROM GPIB

          ON       OFF       ON    BOOT FROM RS232 DCE#1

          ON       ON        OFF   BOOT FROM RS232 DCE#2

          ON       ON        ON    BOOT FROM RS232 (DTE)

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3.0       MEMORY and I/O MAP

     3.1  MEMORY MAP

          The standard ESS Master card has 32K bytes of ram starting  at

0  with the option to increase the RAM size to 48K bytes.The memory  map

of the ESS Master card is as follows

     LOCATION

     0000-07FF    RAM OR 2716 BOOT PROM IF ENABLED

     0800-7FFF    RAM

               OR

     0000-0FFF    RAM or two 2716 or one 2732 BOOT PROM IF ENABLED

     1000-7FFF    RAM

               OR

     0000-1FFF    RAM or two 2732 BOOT PROMs if enabled

     2000-7FFF    RAM



     8000-BFFF    OPTIONAL RAM 16K BYTES



     C000-FFFF    MEMORY MAPPED I/O ACCESS TO THE MASTER BUS 16K BYTES



     3.2  I/O MAP

          The I/O address map for this card is as follows.



     ADDRESS

     00-03H    Z80 DUART 0 RS449 AND RS232 DTE SERIAL PORT

     04-07H    Z80 DUART 1 RS232 AND RS232 DCE SERIAL PORTS

     08-0BH    9513 TIMER 0 BAUD RATE GENERATOR and INTERVAL TIMER

     0C-0FH    9513 TIMER 1 INTERVAL TIMER

     10-13H    9519 INTERRUPT CONTROLLER 0 (INTERRUPTS 1-8)

     14-17H    9519 INTERRUPT CONTROLLER 1 (INTERRUPTS 9-16)

     18-1BH    LINK TO HIP DATA PORT

     1C-1FH    NOT USED RESERVED

     20-27H    9914 GPIB CONTROLLER

     28-3FH    NOT USED RESERVED

     40-4FH    9517 DMA CONTROLLER

     50H WRITE LED STATUS PORT

     51H WRITE NOT USED RESERVED

     52                                                                         
                                                               56H WRITE HIP
     COMMAND PORT

     57H WRITE NOT USED RESERVED



     50H READ  BAUD SELECT SWITCHES

     51H READ  CONFIGURATION SELECT SWITCHES

     52H READ  BACK PANEL SWITCHES

     53H READ  READ BACK CONTROL PORT

     54H READ  READ BACK Z80 ADDRESS EXTEND

     55H READ  READ BACK DMA ADDRESS EXTEND

     56H READ  HIP STATUS PORT

     57H READ  NOT USED RESERVED

     58H-FFH    I/O ACCESS TO MASTER BUS



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4.0 ESS MASTER CARD CHECKOUT



     There are two requirements to the checkout.  The first is to insure

that each submodule of the design performs its function in all operating

modes. The second is to insure the ESS master card performs its function

in the system.



     4.1 CHECKING OUT THE REV 01 PCB



     The  logic  blocks  of the ESS master will be checked  out  in  the

following order.



          1     Check  the 20MHz and 24MHz oscillators and  dividers  to

insure  each  of  the frequencys is correct and go  to  the  appropriate

places.

          2     Check that the Power on Reset enables the BOOT PROM  and

that  the status port LEDs are on.  This is accomplished by seeing  that

the  BOOT PROM is mapped into the memory space and can execute a  simple

program.

          3     Check  that the Dynamic RAM memory is accessed  from  0-

BFFFH  and  that  the wait state generator is working.  Check  that  the

refresh  is working and that the memory can store data when accessed  as

both  program and data memory.  Check that the parity  interrupt  works.

Check that the DMA controller can do memory to memory transfers.

          4     Check  that  the  BAUD  generator  outputs  the  correct

frequencies  at  all baud rates.  Check that the RS232 serial port  will

operate  with a terminal and will generate interrupts on  status  change

and receive data and transmitter empty.

               Check  that the RS449 port will operate with ACORN at all

BAUD  rates.  Check  that it is possible to DMA to and  from  the  RS449

serial port. Check that the RS449 port generates interrupts.

               Check  that  the RS232 (DTE) port operates with  the  DMA

controller.

          5     Check  that the system timer can be programmed and  will

generate interrupts.

          6     Check that the IEEE 488 interface can be programmed  and

talks to ACORN. Check that the GPIB can do DMA transfers.

          7     Check that the high speed link to ACORN  transfers  data

and generates interrupts and operates with the DMA controller.

          8     Using  the STATIC RAM card insure that  the  MASTER  BUS

interface  is  working and that the address extension ports are  working

using the DMA controller and the Z80 to access the MASTER BUS.



**** AT THIS POINT THE REV 01 PC WORKS ***



     4.2  SYSTEM INTEGRATION

          System  integration testing of the ESS MASTER will insure that

the  ESS MASTER works correctly with the HIP processor and the  rest  of

the ESS subsystem cards and software.



.pa

**********************************************************************

*SECTION 5 IS SUBJECT TO CHANGE

**********************************************************************

5.0  BOOT/DIAGNOSTIC MONITOR PROGRAM

     The   BOOT/DIAGNOSTIC   monitor  program  performs  the   following

functions.

     1    Sets memory parity

     2    initializes the I/O devices

     3    performs a confidence test in memory and I/O

     4    BOOTs the system from one of the I/O devices



     5.1  The first function of the BOOT PROM is to checksum itself  and

initialize  the  memory parity and reset the MASTER BUS and  Local  I/O.

Memory  parity is initialized by reading the memory and writing back the

value  found from location 0-BFFFH.  The local I/O and MASTER BUS  reset

bits in the control port are turned on for 1mSec. The checksum is the 16

bit sum of all bytes in the PROM except two.  The last bytes of the prom

are
defi                                                                            
                                                    TE N-1  CHECKSUM LSB

     BYTE N    CHECKSUM MSB



     5.2 The I/O devices are initialized as follows.

     5.2.1 INTERRUPT CONTROLLER

     5.2.2 SYSTEM TIMER AND BAUD RATE GENERATOR

     5.2.3 SERIAL I/O CHANNELS

     5.2.4 IEEE 488 (GPIB)

     5.2.5 DMA CONTROLLER

     5.2.6 PARALLEL LINK TO ACORN



     5.3 CONFIDENCE TEST

     The  confidence  test will turn off a LED in the Status port  if  a

test passes.  The LEDs are turned off in the order 0-7. If all the tests

pass the BOOT program will be executed.  The confidence will report over

the  link  the  completion of each test and whether the test  passed  or

failed.  The  following  tests  are fatal and no boot  will  occur  prom

checksum and bad stack ram.



     5.3.1 MEMORY TESTS

     The memory tests are the BOOT PROM checksum and the RAM tests.  The

RAM  memory test consists of testing each 16K byte bank of  memory.  The

first bank to be tested will be 4000H-7FFFH. Then the test will be moved

to  the 4000H address and the BOOT turned off and the bank from  0-3FFFH

will be tested. The last bank addresses (8000-BFFFH) will only be tested

if  the  status switch indicates a 48K memory system.  The  memory  test

fails  if the read data does not match the written data or if  a  parity

error  interrupt is detected.The memory test will consist of writing and

reading the following patterns and their complements to memory.



     PATTERNS 55H,00H,01H,02H,04H,08H,10H,20H,40H,80H



     5.3.2 SERIAL I/O TESTS

     The  serial I/O tests consist of writing a character string to  the

DART and receiving the same string back under interrupt control. In this

test  the serial ports are wrapped back by setting the wrap back bit  in

the control port.



     5.3.3 IEEE 488 (GPIB)

     Test to be determined.



     5.3.4 DMA TEST

     The  DMA controller will be programmed to move a block  of  memory.

The processor will assure that the move was successful.



     5.3.5 TIMER TEST

     The  timer will be programmed to give an interrupt in 2mSec and the

Z80  will  begin  a timing loop.  The test passes if  the  interrupt  is

received and the timing loop is between 1.9xmSEc and 2.0xmSec.



     5.4 BOOT SEQUENCE

     During the BOOT sequence all messages are sent in the ESS  protocol

format. The host must send the "/U*00" message after it receives the ESS

wake-up interrupt. For message formats see document #xxxxxxxxx.

     If  all of the confidence tests pass the ESS master will enter  the

BOOT  sequence.  The  BOOT sequence begins by reading the  CONFIGURATION

input port and testing bits 0 and 1 to determine where to boot from. The

initial  program loaded by the BOOT must be above 2000H to insure it  is

out  of  the  way  of the BOOT PROM address  space.  One  of  the  first

functions  of the program loaded will be to disable the BOOT  PROM.  The

BOOT  will  load a standard INTEL format Hex file.  It will  report  the

following  errors.  Character  not  ASCII hex (0-9,A-F)  in  data,record

type,address,byte count or checksum fields. Checksum error. Memory write

error  (the data written to memory cannot be read back).  Have  received

128  characters and have not detected a start of record  character  (:).

The format of the records the loader processes is as follows.



     RECORD FORMAT

     1 2 4 2 2xn 2 2  number of characters per field position

     ! ! ! ! !   ! !- EOL CHARACTERS

     ! ! ! ! !   !--- CHECKSUM

     ! ! ! ! !------- DATA

     ! ! ! !--------- RECORD TYPE

     ! ! !----------- ADDRESS

     ! !------------- BYTE COUNT

     !--------------- START OF RECORD CHARACTER



1. The START OF RECORD CHARACTER IS A ':'.

2.  The  BYTE COUNT is the number of bytes in the data block.  The  byte

count uses two hexadecimal digits.

3.  The  ADDRESS  is  four  hexadecimal digits and  gives  the  starting

location of the data block in memory.

4.  The RECORD
T                                                                               
                                                 der

will assume all records are of type 0 and will detect end of file when a

record  of  0 BYTE COUNT is detected.  The loader will then jump to  the

address contained in the record with 0 byte count.

5. The DATA consists of two hexadecimal digits per data byte.

6.  The CHECKSUM consists of two hexidecimal digits. The CHECKSUM is the

negitive sum of all the eight bit bytes in the record (modulo 256).  The

CHECKSUM  includes  the BYTE COUNT,ADDRESS,RECORD TYPE and DATA  fields.

The sum of all bytes in the record including the checksum should be 0.

7.  The EOL characters are ignored by the loader. The EOL characters are

normally a carrage return and line feed.

.pa

6.0 FUNCTIONS OF SWITCHES AND JUMPERS ON THE ESS MASTER CARD

     6.1 FUNCTIONS OF JUMPERS

          W1 A-B CLOSED       GPIB DATA BUS OPEN COLLECTOR

          W1 A-B OPEN         GPIB DATA BUS TRISTATE



          W2 A,B,C OPEN       GPIB 'REN AND IFC' RECEIVED

          W2 A-B CLOSED       GPIB 'REN AND IFC' TRANSMIT

          W2 A-C CLOSED       GPIB 'REN AND IFC' CONTROLLED BY 'DC'



          W3 A-B CLOSED       MEMORY PARITY INTERRUPT ENABLED

          W3 B-C CLOSED       MEMORY PARITY INTERRUPT DISABLED



          W4 D-E,A-B CLOSED   2716 2KX8 BOOT PROM

          W4 E-F,B-C CLOSED   2732 4KX8 BOOT PROM



          W5 A-B,C-D  CLOSED  IORC COMMAND TO MASTER BUS



          W6 A-B CLOSED,C-D OPEN  MASTER BUS INIT/ OUTPUT THIS CARD

          W6 A-B OPEN,C-D CLOSED  MASTER BUS INIT/ INPUT THIS CARD



          W7-W20 A-B CLOSED   PLACE TO SCRAMBLE INTERRUPT PRIORITY

          W32,W33 A-B CLOSED  PLACE TO SCRAMBLE INTERRUPT PRIORITY



          W21 A-B CLOSED RX CLK FOR RS449 PORT FROM BAUD 1

          W21 B-C CLOSED RX CLK FOR RS449 PORT FROM 'RT' SIGNAL

          W22 A-B CLOSED TX CLK FOR RS449 PORT FROM BAUD 1

          W22 B-C CLOSED TX CLK FOR RS449 PORT FROM 'ST' SIGNAL

          W23 A-B,C-D CLOSED ENABLE BAUD 1 TO RS449 SIGNAL 'TT'



          W24 A-B CLOSED A1 TO FPLA

          W25 A-B CLOSED A2 TO FPLA



          W24 A-B CLOSED DEFEAT AUTO REFRESH ON RAMS



          W26 A-B CLOSED MEMORY XAK IS XACK

          W26 B-C CLOSED MEMORY XAK IS SACK



          W27 A-B,C-D IOWC TO MASTER BUS

          W28 A-I     WAIT STATE TO HIP PROCESSOR DURING INTERRUPT



          W29 A-B CLOSED BOOT PROM 0 IS 2K 2716 ADDRESS 0-7FFH

              A-C CLOSED BOOT PROM 0 IS 4K 2732 ADDRESS 0-FFFH



          W30 A-B CLOSED BOOT PROM 1 IS 2K 2716 ADDRESS 800H-FFFH

              A-C CLOSED BOOT PROM 1 IS 4K 2732 ADDRESS 1000H-1FFFH



          W31 A-B CLOSED BOOT PROM ADDRESS SPACE IS 2K 0-7FFH

              A-C CLOSED BOOT PROM ADDRESS SPACE IS 4K 0-FFFH

              A-D CLOSED BOOT PROM ADDRESS SPACE IS 8K 0-1FFFH



.PA

     6.2 LIST OF TERMINAL CONNECTIONS



          E1-E8     OUTPUT OF WAIT GENERATOR

          E9        WAIT STATE SELECT FOR BOOT PROM

          E10       OPTIONAL WAIT INPUT FOR LOCAL I/O ACCESS

          E11       OPTIONAL WAIT INPUT FOR INTA CYCLE

          E12-13    TIE POINT FOR DMAALE TO ANYSTB

          E14       UNUSED INPUT TO ANYSTB

          E15       BIT 0 OF HIP COMMAND PORT (NOT READABLE)

          E16       BIT 5 OF HIP COMMAND PORT

          E17       BIT 6 OF HIP COMMAND PORT

          E18       BIT 7 OF HIP COMMAND PORT (NOT READABLE)

          E21       FOUT OF TIMER 0

          E22       FOUT OF TIMER 1

          E23       UNUSED INPUT TO FPLA

          E24       UNUSED OUTPUT FROM FPLA

          E25       BIT 1 OF Z80 ADDRESS EXTEND

          E26       BIT 0 OF Z80 ADDRESS EXTEND

          E27       BIT 1 OF DMA ADDRESS EXTEND

          E28       BIT 0 OF DMA ADDRESS EXTEND

          E29       TIE POINT FOR A7 OF 64K DYNAMIC RAM

          E30       TIE POINT FOR GROUND NEAR FPLA

.PA

     6.3 LIST OF TEST POINTS



          TP1       ANY STROBE (MRD+MWR+INTACK+IORD+IOWR)

          TP2       WAIT

          TP4       10MHZ CCLK

                                                                                                                                P8       10MHZ
                                                                                                                                
          TP9       5MHZ

          TP10      8MHZ

          TP11      4MHZ INVERTED

          TP12      2MHZ

          TP13      1MHZ

          TP14      6MHZ

          TP15      3MHZ

          TP16      24MHZ TO MEMORY

          TP17      4MHZ TO Z80 AND DARTS

          TP18      4MHZ TO DMA AND WAIT

          TP20      BAUD RATE 1 RS449 DTE

          TP21      BAUD RATE 2 RS232 DTE

          TP22      BAUD RATE 3 RS232 DCE

          TP23      BAUD RATE 4 RS232 DCE

          TP24      TIMER INTERRUPT 0

          TP26      TIMER INTERRUPT 1

          TP27      TIMER INTERRUPT 2

          TP28      TIMER INTERRUPT 3

          TP29      TIMER INTERRUPT 4

          TP30      TIMER INTERRUPT 5



.PA

7.0 LIST OF CONNECTORS AND PINOUT



     7.1 MASTER BUS P1

PIN

01   +5V

02   +5V

03   +5V

04   +5V

05   +12V

06   +12V

07   -12V

08   -12V

09   -5V

10   -5V

11   GND

12   GND

13   INIT/     RESET

14   -5V

15   MRDC/     MEMORY READ COMMAND

16   -5V

17   MWTC/     MEMORY WRITE COMMAND

18   GND

19   XACK/     TRANSFER ACKNOWLEGE

20   INH1/     INHIBIT 1, DISABLE RAM

21   INT1/     INTERRUPT 1

22   IORC/     I/O READ COMMAND

23   AD10/

24   AD11/

25   CCLK/     CONSTANT CLOCK (10MHZ)

26   GND

27   AD12/

28   AD13/

29   INT5/     INTERRUPT 5 (ESS)

30   IOWC/     I/O WRITE COMMAND

31   GND

32   GND

33   ADRE/

34   ADRF/

35   ADRC/

36   ADRD/

37   ADRA/

38   ADRB/

39   ADR8/

40   ADR9/

41   ADR6/

42   ADR7/

43   ADR4/

.PA

PIN

44   ADR5/

45   ADR2/

46   ADR3/

47   ADR0/

48   ADR1/

49   GND

50   GND

51   DAT6/

52   DAT7/

53   DAT4/

54   DAT3/

55   DAT2/

56   DAT3/

57   DAT0/

58   DAT1/

59   GND

60   GND

.PA

     7.2 MASTER BUS P2 CONNECTOR MASTER I/O

PIN

01   DM'  IN   DATA MODE RS449

02   DM

03   CS'  IN   CLEAR TO SEND RS449

04   CS

05   RD'  IN   RECEIVE DATA RS449

06   RD

07   RR   IN   RECEIVER READY RS449

08   RR'

09   ST   IN   SEND TIMING    RS449

10   ST'

11   RT   IN   RECEIVE TIMING RS449

12   RT'

13   SD   OUT  SEND DATA      RS449

14   SD'

15   RS'  OUT  REQUEST TO SEND     RS449

16   RS

17   TR'  OUT  TERMINAL READY RS449

18   TR

19   TT   OUT  TERMINAL TIMING RS449

20   TT'

21   GND

22   GND

23   DSR1 IN   DATA SET READY RS232 DTE

24   RXD1 IN   RECEIVE DATA RS232 DTE

25   TXD1 OUT  TRANSMIT DATA RS232 DTE

26   CTS1 IN   CLEAR TO SEND RS232 DTE

27   DTR1 OUT  DATA TERMINAL READY RS232 DTE

28   RSLD1 IN  CARRIER DETECT RS232 DTE

29   RTS1 OUT  REQUEST TO SEND RS232 DTE

30   GND

31   GND

32   GND

33   GND

34   GND

35   RTS2 IN   REQUEST TO SEND RS232 DCE#1

36   DTR2 IN   DATA TERMINAL READY RS232 DCE#1

37   GND

38   TXD2 IN   TRANSMIT DATA RS232 DCE#1

39   GND

40   GND

41   GND

42   GND

43   STRTSYNC

44

45

46

47

48   BKLINK

49   +5V

50   +5V

.PA



PIN

51   BKNOW

52

53

54

55

56

57   GND

58   GND

59   GND

60   GND

61   RXD2 OUT  RECEIVE DATA RS232 DCE#1

62   RSLD2 OUT CARRIER DETECT RS232 DCE#1

63   CTS2 OUT  CLEAR TO SEND RS232 DCE#1

64   DSR2 OUT  DATA SET READY RS232 DCE#1

65   GND

66   GND

67   GND

68   GND

69   TXD3 IN   TRANSMIT DATA RS232 DCE#2

70   DTR3 IN   DATA TERMINAL READY RS232 DCE#2

71   GND

72   RTS3 IN   REQUEST TO SEND RS232 DCE#2

73   GND

74   GND

75   GND

76   GND

77   RXD3 OUT  RECEIVE DATA RS232 DCE#2

78   RSLD3 OUT CARRIER DETECT RS232 DCE#2

79   CTS3 OUT  CLEAR TO SEND RS232 DCE#2

80   DSR3 OUT  DATA SET READY RS232 DCE#2

81   GND

82   GND

83   GND

84   GND

85   GND

86   GND

87   DIO2      GPIB DATA 2

88   DIO1      GPIB DATA 1

89   DIO4      GPIB DATA 4

90   DIO3      GPIB DATA 3

91   DIO6      GPIB DATA 6

92   DIO5      GPIB DATA 5

93   DIO8      GPIB DATA 8

94   DIO7      GPIB DATA 7

95   GND

96   GND

97   GND

98   GND

99   IFC       GPIB INTERFACE CLEAR

100  REN       GPIB REMOTE ENABLE

.PA



PIN

101  NRFD      GPIB NOT READY FOR DATA

102  NDAC      GPIB NOT DATA
A                                                                               
                                                       GPIB ATTENTION

107  GND

108  GND

109  GND

110  GND

111  BSW1 IN   BACK PANEL BAUD SWITCH 1

112  BSW2 IN   BACK PANEL BAUD SWITCH 2

113  BSW0 IN   BACK PANEL BAUD SWITCH 0

114  GSW1 IN   BACK PANEL GPIB ADDRESS SWITCH 1

115  GSW2 IN   BACK PANEL GPIB ADDRESS SWITCH 2

116  GSW3 IN   BACK PANEL GPIB ADDRESS SWITCH 3

117  GSW4 IN   BACK PANEL GPIB ADDRESS SWITCH 4

118  GSW5 IN   BACK PANEL GPIB ADDRESS SWITCH 5

119  GND

120  GND

121  GND

122  GND

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143  NMISW     IN   NMI INTERRUPT INPUT

144  RESETSW   IN   MASTER RESET SWITCH

145  GND

146  GND

147  +5V

148  +5V

149  +5V

150  +5V

.PA



PIN

151  TRCLK0

152  TRCLK1

153  TRCLK2

154  TRCLK3

155

156

157  UEVT0

158  UEVT1

159  UEVT2

160  UEVT3



.PA

     7.3 HIP INTERFACE (ACORN I/O EXPANDER) P3

PIN

01   GND

02   IODB1

03   RESET

04   IODB0

05   DMAREQ

06   IODB4

07   DMAGNT

08   IODB5

09   GND

10   IODB6

11   GND

12   IODB3

13   GND

14   IODB2

15   GND

16   IODB7

17   GND

18   LM1

19   GND

20   LIORQ

21   GND

22   LRD

23   GND

24   LWR

25   GND

26   DMAEI

27   GND

28   XPEI

29   GND

30   PINT

31   GND

32   MOS CLK 4MHZ

33   GND

34   WAIT

35   GND

36   LAD7

37   GND

38   LAD0

39   GND

40   LAD1

41   GND

42   LAD2

43   GND

44   LAD3

45   GND

46   LAD4

47   GND

48   LAD5

49   GND

50   LAD6

.PA

8.0  MESSAGES



8.1  MESSAGES RECEIVED FROM HOST



     HOST READY MESSAGE IS THE CHARACTER SEQUENCE  /U*00

     HEX LOADER MESSAGES

          DATA BLOCK :lnaddr00data...ckCRLF

          EOF  BLOCK :00addr00ckCRLF  or :00addr01ckCRLF

                         ln= number of data bytes in hex

                       addr= address of data block or program start addr

                       data= data two char/byte

                         ck= checksum



8.2  MESSAGES TRANSMITTED TO THE HOST



     All messages transmitted to the host have the following format.



     byte count                  2 bytes

     message opcode              2 bytes    0,op

     reply code/system id        2 bytes of 0

     CRLF                        2 bytes

     message text                n bytes

     checksum                    1 byte



     The opcode byte has the following values.



     TEST PROGRESS OPCODES



     STP  EQU  0AH       TEST PASSED

     STF  EQU  0BH       TEST FAILED

     STC  EQU  0CH       TEST COMPLETE



     HEX LOADER OPCODES



     SFH  EQU  04H       CHAR NOT ASCII HEX (0-9,A-F)

     SFC  EQU  05H       CHECKSUM ERROR ON RECEIVED RECORD

     SFW  EQU  06H       MEMORY WRITE ERROR

     SFN  EQU  07H       NO START OF RECORD AFTER RECEIVING 127 CHARS

     SFR  EQU  08H       IMPROPER RECORD TYPE



MESSAGES FROM SELF TEST



TYPE      TEXT

STP       ESS BOOT VERS x.y

          CKSUM,STK RAM,TIMER OK



STP       RAM OK 16K-32K



STP       RAM OK 0-16K



STP       DMA TEST OK



STP       SW1 = xx SW2 = yy SW4 = zz



STP       RAM OK 32K-48K



TYPE      TEXT



STP       NO RAM 32K-48K



STF       FAIL RAM TEST ADR=xxxx BIT=yy



STF       FAIL DMA TEST NO INTERRUPT



STF       FAIL DMA TEST ADR=xxxx BIT=yy



STF       FAIL TIMER TEST



STF       UNEXPECTED INTERRUPT xx



STF       FAIL PORT TEST PORT=xx BIT=yy

.PA

HEX LOADER MESSAGES



TYPE      TEXT

STC       HEX LOADER RDY



SFH       HEX LDR INVALID ASCII HEX CHAR



SFC       HEX LDR CKSUM ERROR



SFW       HEX LDR WRITE ERR ADR=xxxx BIT=yy



SFN       HEX LDR NO START OF RECORD



SFR       HEX LDR BAD RECORD TYPE

