# This is a maptable for nelsis <--> seadif conversion, generated/maintained by 'nelsea'
# Written on: Wed Mar 25 11:56:19 1992
# You can edit this file to control the mapping process
# Each line contains the name of a nelsis cell and its corresponding seadif cell
# The status field may contain the following values:
#    'written'       the cell was succesfully written into seadif resp. nelsis
#    'primitive'     the cell is a primitive which should not be read or converted
#    [anything else] the cell will be written if necessary
# To check the consistency of this table: use 'nelsea -C'
#    N E L S I S     |                   S E A D I F                     | nelsis->sdf sdf->nelsis
# view    cellname   | library      function     circuit      layout     |   status      status
#--------------------+---------------------------------------------------+------------------------
 layout   buf20        oplib12_92       buf20        buf20        buf20
 circuit  Buf20        oplib12_92       buf20        buf20        $dummy
 layout   dfr11        oplib12_92       dfr11        dfr11        dfr11
 circuit  Dfr11        oplib12_92       dfr11        dfr11        $dummy
 layout   dfr10        oplib12_92       dfr10        dfr10        dfr10
 circuit  Dfr10        oplib12_92       dfr10        dfr10        $dummy
 layout   lab10        oplib12_92       lab10        lab10        lab10 
 circuit  Lab10        oplib12_92       lab10        lab10        $dummy 
 layout   lah10        oplib12_92       lah10        lah10        lah10  
 circuit  Lah10        oplib12_92       lah10        lah10        $dummy 
 layout   dfn20        oplib12_92       dfn20        dfn20        dfn20 
 circuit  Dfn20        oplib12_92       dfn20        dfn20        $dummy 
 layout   no310        oplib12_92       no310        no310        no310 
 circuit  No310        oplib12_92       no310        no310        $dummy 
 layout   no210        oplib12_92       no210        no210        no210  
 circuit  No210        oplib12_92       no210        no210        $dummy  
 layout   na210        oplib12_92       na210        na210        na210   
 circuit  Na210        oplib12_92       na210        na210        $dummy   
 layout   iv110        oplib12_92       iv110        iv110        iv110  
 circuit  Iv110        oplib12_92       iv110        iv110        $dummy  
 layout   na310        oplib12_92       na310        na310        na310   
 circuit  Na310        oplib12_92       na310        na310        $dummy  
 layout   tg111        oplib12_92       tg111        tg111        tg111   
 circuit  tg111        oplib12_92       tg111        tg111        $dummy  
 layout   de210        oplib12_92       de210        de210        de210   
 circuit  De210        oplib12_92       de210        de210        $dummy  
 layout   de211        oplib12_92       de211        de211        de211   
 circuit  De211        oplib12_92       de211        de211        $dummy  
 layout   laa10        oplib12_92       laa10        laa10        laa10   
 circuit  Laa10        oplib12_92       laa10        laa10        $dummy  
 layout   mu110        oplib12_92       mu110        mu110        mu110   
 circuit  Mu110        oplib12_92       mu110        mu110        $dummy  
 layout   mu111        oplib12_92       mu111        mu111        mu111   
 circuit  Mu111        oplib12_92       mu111        mu111        $dummy  
 layout   mu210        oplib12_92       mu210        mu210        mu210   
 circuit  Mu210        oplib12_92       mu210        mu210        $dummy  
 layout   rer10        oplib12_92       rer10        rer10        rer10   
 circuit  Rer10        oplib12_92       rer10        rer10        $dummy  
 layout   col10        oplib12_92       col10        col10        col10   
 circuit  Col10        oplib12_92       col10        col10        $dummy  
 layout   ln3x3	       oplib12_92       ln3x3        ln3x3        ln3x3
 circuit  ln3x3        oplib12_92       ln3x3        ln3x3     
 layout   lp3x3	       oplib12_92       lp3x3        lp3x3        lp3x3
 circuit  lp3x3        oplib12_92       lp3x3        lp3x3     
 layout   mir_nin      oplib12_92      mir_nin        mir_nin    mir_nin
 circuit  mir_nin      oplib12_92      mir_nin        mir_nin    mir_nin
 layout   mir_pin      oplib12_92      mir_pin        mir_pin    mir_pin
 circuit  mir_pin      oplib12_92      mir_pin        mir_pin    mir_pin
 layout   mir_nout      oplib12_92      mir_nout        mir_nout    mir_nout
 circuit  mir_nout      oplib12_92      mir_nout        mir_nout    mir_nout 
 layout   mir_pout      oplib12_92      mir_pout        mir_pout    mir_pout
 circuit  mir_pout      oplib12_92      mir_pout        mir_pout    mir_pout


