#
# 68k_test_7
#
# seventh test file for the 68k core testing program
#
# tests SUB/SUBA/SUBX instructions in the 0x9xxx range
#

# $Id$

#
# NOTE: Someone plays fast and loose with flags...
#

# test SUB.B d0, d1
start sub.b d0, d1, take 1
set mem 0x002000 = 0x9200
set reg d0 = 0x00000000
set reg d1 = 0x00000000
set pc 0x002000
set flags 0x0000
set cycles 4
run
check reg d1 = 0x00000000
check pc 0x002002
check flags 0x0004
check cycles 0
done

# test SUB.B d0, d1
start sub.b d0, d1, take 2
set mem 0x002000 = 0x9200
set reg d0 = 0x00000000
set reg d1 = 0x00000001
set pc 0x002000
set flags 0x0000
set cycles 4
run
check reg d1 = 0x00000001
check pc 0x002002
check flags 0x0000
check cycles 0
done

# test SUB.B d0, d1
start sub.b d0, d1, take 3
set mem 0x002000 = 0x9200
set reg d0 = 0x00000001
set reg d1 = 0x00000000
set pc 0x002000
set flags 0x0000
set cycles 4
run
check reg d1 = 0x000000ff
check pc 0x002002
check flags 0x0019
check cycles 0
done

# test SUB.B d0, d1
start sub.b d0, d1, take 4
set mem 0x002000 = 0x9200
set reg d0 = 0x000000ff
set reg d1 = 0x00000000
set pc 0x002000
set flags 0x0000
set cycles 4
run
check reg d1 = 0x00000001
check pc 0x002002
check flags 0x0011
check cycles 0
done

# test SUB.W d0, d1
start sub.w d0, d1, take 1
set mem 0x002000 = 0x9240
set reg d0 = 0x00000000
set reg d1 = 0x00000000
set pc 0x002000
set flags 0x0000
set cycles 4
run
check reg d1 = 0x00000000
check pc 0x002002
check flags 0x0004
check cycles 0
done

# test SUB.W d0, d1
start sub.w d0, d1, take 2
set mem 0x002000 = 0x9240
set reg d0 = 0x00000000
set reg d1 = 0x00000001
set pc 0x002000
set flags 0x0000
set cycles 4
run
check reg d1 = 0x00000001
check pc 0x002002
check flags 0x0000
check cycles 0
done

# test SUB.W d0, d1
start sub.w d0, d1, take 3
set mem 0x002000 = 0x9240
set reg d0 = 0x00000001
set reg d1 = 0x00000000
set pc 0x002000
set flags 0x0000
set cycles 4
run
check reg d1 = 0x0000ffff
check pc 0x002002
check flags 0x0019
check cycles 0
done

# test SUB.W d0, d1
start sub.w d0, d1, take 4
set mem 0x002000 = 0x9240
set reg d0 = 0x0000ffff
set reg d1 = 0x00000000
set pc 0x002000
set flags 0x0000
set cycles 4
run
check reg d1 = 0x00000001
check pc 0x002002
check flags 0x0011
check cycles 0
done

# test SUBA.W d0, a0
start suba.w d0, a0, take 1
set mem 0x002000 = 0x90c0
set reg d0 = 0x00000000
set reg a0 = 0x00000000
set pc 0x002000
set cycles 8
run
check reg a0 = 0x00000000
check pc 0x002002
check cycles 0
done

# test SUBA.W d0, a0
start suba.w d0, a0, take 2
set mem 0x002000 = 0x90c0
set reg d0 = 0x00000001
set reg a0 = 0x00000000
set pc 0x002000
set cycles 8
run
check reg a0 = 0xffffffff
check pc 0x002002
check cycles 0
done

# test SUBA.L d0, a0
start suba.l d0, a0, take 1
set mem 0x002000 = 0x91c0
set reg d0 = 0x00000000
set reg a0 = 0x00000000
set pc 0x002000
set cycles 8
run
check reg a0 = 0x00000000
check pc 0x002002
check cycles 0
done

# test SUBA.L d0, a0
start suba.l d0, a0, take 2
set mem 0x002000 = 0x91c0
set reg d0 = 0x00010001
set reg a0 = 0x00000000
set pc 0x002000
set cycles 8
run
check reg a0 = 0xfffeffff
check pc 0x002002
check cycles 0
done

#
# $Log$
#
