The following items are known to be problems in the current code that need to be fixed
or features that are unimplemented/not complete that need to be done.

Legend
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X   = This feature/fix has been completed and tested
IP  = In Progress

Score command
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   1.  Add ability for user to specify FSM all possible states/state transitions
       for a particular FSM on a command-line basis.

   2.  Add ability to automatically extract all possible states/state transitions
       for a specified FSM.

   3.  Add ability to automatically locate and extract an FSM from the design
       without user intervention.

   4.  Add more Verilog-2001 constructs to parser.
	- automatic storage for functions/tasks (instead of static) - difficult!
	- generate command (extremely low priority)
	- config command

   5.  Allow Covered to run simulation phases in parallel to increase performance.

   6.  Add feature to cause Covered to omit the simulation phase for toggle and
       FSM coverage results.

   7.  Add assertion coverage


Merge command
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   1.  Add ability to merge more than two CDD files with a single command

   2.  Add ability to merge two CDDs from different parts of the same design


Report command
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   1.  Add assertion coverage


Miscellaneous
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IP 1.  Add regression that produces known, achievable error conditions in the code.


GUI
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   1.  Add FSM coverage output

   2.  Add ability to turn on/off coverage points and have coverage information automatically adjusted.

   3.  Add assertion coverage output
